[RISCV] Support 'f' Inline Assembly Constraint
[llvm-core.git] / test / CodeGen / AMDGPU / hazard-buffer-store-v-interp.mir
blob8cc294f57b2680c8851a09cee8d52109ee272298
1 # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
2 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
4 # GCN-LABEL: name: hazard_buffer_store_v_interp
5 # GCN:    bb.0.entry:
6 # GCN-NEXT:    BUFFER_STORE_DWORDX4_OFFSET_exact
7 # GCN-NEXT:    S_NOP
8 # GCN-NEXT:    V_INTERP_P1_F32
10 name:            hazard_buffer_store_v_interp
11 body:             |
12   bb.0.entry:
13     liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
14   
15     BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, 0, implicit $exec
16     $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
17     S_ENDPGM 0
19 ...