| commit | 5018f6ea8fcd1c655d36a2ae1900e0ccee906b96 | |
| author | Craig Topper <craig.topper@intel.com> | |
| Tue, 20 Nov 2018 04:30:26 +0000 (20 04:30 +0000) | ||
| committer | Craig Topper <craig.topper@intel.com> | |
| Tue, 20 Nov 2018 04:30:26 +0000 (20 04:30 +0000) | ||
| tree | 21be267d2393f657371006ec4144da6c766cd86b | treesnapshot (tar.gz zip) |
| parent | c947a215ea23c30056bf7d1166e0b5ec05c5232f | commitdiff |
[SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks
Summary:
We already support this for scalars, but it was explicitly disabled for vectors. In the updated test cases this allows us to see the upper bits are zero to use less multiply instructions to emulate a 64 bit multiply.
This should help with this ispc issue that a coworker pointed me to https://github.com/ispc/ispc/issues/1362
Reviewers: spatel, efriedma, RKSimon, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D54725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347287 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
We already support this for scalars, but it was explicitly disabled for vectors. In the updated test cases this allows us to see the upper bits are zero to use less multiply instructions to emulate a 64 bit multiply.
This should help with this ispc issue that a coworker pointed me to https://github.com/ispc/ispc/issues/1362
Reviewers: spatel, efriedma, RKSimon, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D54725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347287 91177308-0d34-0410-b5e6-96231b3b80d8
| lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | diffblobblamehistory | |
| lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | diffblobblamehistory | |
| test/CodeGen/X86/vector-mul.ll | diffblobblamehistory |