| commit | f343dcd487169c85fc73f0e2c1cf5995a99cd55d | |
| author | David Green <david.green@arm.com> | |
| Sun, 15 Sep 2019 14:14:47 +0000 (15 14:14 +0000) | ||
| committer | David Green <david.green@arm.com> | |
| Sun, 15 Sep 2019 14:14:47 +0000 (15 14:14 +0000) | ||
| tree | 96eca6058efa7e751a8586a6574f808fa53391ba | treesnapshot (tar.gz zip) |
| parent | 71f28d66ddfc9e9692ba9d11e3d2c0401ca1a0ae | commitdiff |
[ARM] Masked loads and stores
Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc, and so is
currently behind an option.
The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.
Differential Revision: https://reviews.llvm.org/D67186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371932 91177308-0d34-0410-b5e6-96231b3b80d8
Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc, and so is
currently behind an option.
The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.
Differential Revision: https://reviews.llvm.org/D67186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371932 91177308-0d34-0410-b5e6-96231b3b80d8