1 //===- AMDGPUGenRegisterBankInfo.def
-----------------------------*- C
++ -*-==//
3 // Part of the LLVM Project
, under the Apache License v2.0 with LLVM Exceptions.
4 // See https
://llvm.org
/LICENSE.txt for license information.
5 // SPDX
-License
-Identifier
: Apache
-2.0 WITH LLVM
-exception
7 //===----------------------------------------------------------------------===//
9 /// This file defines all the static objects used by AMDGPURegisterBankInfo.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
16 enum PartialMappingIdx
{
57 const RegisterBankInfo
::PartialMapping PartMappings
[] {
58 // StartIdx
, Length
, RegBank
61 {0, 1, SGPRRegBank
}, // SGPR begin
65 {0, 128, SGPRRegBank
},
66 {0, 256, SGPRRegBank
},
67 {0, 512, SGPRRegBank
},
68 {0, 1024, SGPRRegBank
},
70 {0, 1, VGPRRegBank
}, // VGPR begin
74 {0, 128, VGPRRegBank
},
75 {0, 256, VGPRRegBank
},
76 {0, 512, VGPRRegBank
},
77 {0, 1024, VGPRRegBank
},
81 {0, 288, SGPRRegBank
},
82 {0, 288, VGPRRegBank
},
83 {0, 288, AGPRRegBank
},
84 {0, 320, SGPRRegBank
},
85 {0, 320, VGPRRegBank
},
86 {0, 320, AGPRRegBank
},
87 {0, 352, SGPRRegBank
},
88 {0, 352, VGPRRegBank
},
89 {0, 352, AGPRRegBank
},
90 {0, 384, SGPRRegBank
},
91 {0, 384, VGPRRegBank
},
92 {0, 384, AGPRRegBank
},
94 {0, 32, AGPRRegBank
}, // AGPR begin
96 {0, 128, AGPRRegBank
},
97 {0, 256, AGPRRegBank
},
98 {0, 512, AGPRRegBank
},
99 {0, 1024, AGPRRegBank
}
102 const RegisterBankInfo
::ValueMapping ValMappings
[] {
104 {&PartMappings
[0], 1},
107 {&PartMappings
[1], 1}, // 1
108 {nullptr
, 0}, // Illegal power of
2 sizes
111 {&PartMappings
[2], 1}, // 16
112 {&PartMappings
[3], 1}, // 32
113 {&PartMappings
[4], 1}, // 64
114 {&PartMappings
[5], 1}, // 128
115 {&PartMappings
[6], 1}, // 256
116 {&PartMappings
[7], 1}, // 512
117 {&PartMappings
[8], 1}, // 1024
120 {&PartMappings
[9], 1}, // 1
124 {&PartMappings
[10], 1}, // 16
125 {&PartMappings
[11], 1}, // 32
126 {&PartMappings
[12], 1}, // 64
127 {&PartMappings
[13], 1}, // 128
128 {&PartMappings
[14], 1}, // 256
129 {&PartMappings
[15], 1}, // 512
130 {&PartMappings
[16], 1}, // 1024
131 {&PartMappings
[17], 1},
132 {&PartMappings
[18], 1},
133 {&PartMappings
[19], 1},
134 {&PartMappings
[20], 1},
135 {&PartMappings
[21], 1},
136 {&PartMappings
[22], 1},
137 {&PartMappings
[23], 1},
138 {&PartMappings
[24], 1},
139 {&PartMappings
[25], 1},
140 {&PartMappings
[26], 1},
141 {&PartMappings
[27], 1},
142 {&PartMappings
[28], 1},
143 {&PartMappings
[29], 1},
144 {&PartMappings
[30], 1},
145 {&PartMappings
[31], 1},
153 {&PartMappings
[32], 1}, // 32
154 {&PartMappings
[33], 1}, // 64
155 {&PartMappings
[34], 1}, // 128
156 {&PartMappings
[35], 1}, // 256
157 {&PartMappings
[36], 1}, // 512
158 {&PartMappings
[37], 1} // 1024
161 const RegisterBankInfo
::PartialMapping SGPROnly64BreakDown
[] {
162 {0, 32, SGPRRegBank
}, // 32-bit op
163 {0, 32, SGPRRegBank
}, // 2x32
-bit op
164 {32, 32, SGPRRegBank
},
165 {0, 64, SGPRRegBank
}, // <2x32
-bit
> op
167 {0, 32, VGPRRegBank
}, // 32-bit op
168 {0, 32, VGPRRegBank
}, // 2x32
-bit op
169 {32, 32, VGPRRegBank
},
173 // For some instructions which can operate
64-bit only for the scalar
174 // version. Otherwise
, these need to be split into
2 32-bit operations.
175 const RegisterBankInfo
::ValueMapping ValMappingsSGPR64OnlyVGPR32
[] {
176 /*32-bit sgpr
*/ {&SGPROnly64BreakDown
[0], 1},
177 /*2 x
32-bit sgpr
*/ {&SGPROnly64BreakDown
[1], 2},
178 /*64-bit sgpr
*/ {&SGPROnly64BreakDown
[3], 1},
180 /*32-bit vgpr
*/ {&SGPROnly64BreakDown
[4], 1},
181 /*2 x
32-bit vgpr
*/ {&SGPROnly64BreakDown
[5], 2}
184 enum ValueMappingIdx
{
190 const RegisterBankInfo
::ValueMapping
*getValueMapping(unsigned BankID
,
195 if (BankID
== AMDGPU
::VCCRegBankID
)
196 return
&ValMappings
[0];
198 Idx
= BankID
== AMDGPU
::SGPRRegBankID ? PM_SGPR1
: PM_VGPR1
;
202 case AMDGPU
::VGPRRegBankID
:
205 case AMDGPU
::SGPRRegBankID
:
208 case AMDGPU
::AGPRRegBankID
:
211 default
: llvm_unreachable("Invalid register bank");
216 case AMDGPU
::VGPRRegBankID
:
219 case AMDGPU
::SGPRRegBankID
:
222 case AMDGPU
::AGPRRegBankID
:
225 default
: llvm_unreachable("Invalid register bank");
230 case AMDGPU
::VGPRRegBankID
:
233 case AMDGPU
::SGPRRegBankID
:
236 case AMDGPU
::AGPRRegBankID
:
239 default
: llvm_unreachable("Invalid register bank");
244 case AMDGPU
::VGPRRegBankID
:
247 case AMDGPU
::SGPRRegBankID
:
250 case AMDGPU
::AGPRRegBankID
:
253 default
: llvm_unreachable("Invalid register bank");
258 case AMDGPU
::VGPRRegBankID
:
261 case AMDGPU
::SGPRRegBankID
:
264 case AMDGPU
::AGPRRegBankID
:
267 default
: llvm_unreachable("Invalid register bank");
272 case AMDGPU
::VGPRRegBankID
:
275 case AMDGPU
::SGPRRegBankID
:
278 case AMDGPU
::AGPRRegBankID
:
281 default
: llvm_unreachable("Invalid register bank");
283 Idx
+= Log2_32_Ceil(Size
);
287 assert(Log2_32_Ceil(Size
) == Log2_32_Ceil(ValMappings
[Idx
].BreakDown
->Length
));
288 assert(BankID
== ValMappings
[Idx
].BreakDown
->RegBank
->getID());
290 return
&ValMappings
[Idx
];
293 const RegisterBankInfo
::ValueMapping
*getValueMappingSGPR64Only(unsigned BankID
,
296 return
getValueMapping(BankID
, Size
);
298 if (BankID
== AMDGPU
::VGPRRegBankID
)
299 return
&ValMappingsSGPR64OnlyVGPR32
[4];
301 assert(BankID
== AMDGPU
::SGPRRegBankID
);
302 return
&ValMappingsSGPR64OnlyVGPR32
[2];
305 /// Split any
64-bit value into
2 32-bit pieces. Unlike
306 /// getValueMappingSGPR64Only
, this splits both VGPRs and SGPRs.
307 const RegisterBankInfo
::ValueMapping
*getValueMappingSplit64(unsigned BankID
,
310 if (BankID
== AMDGPU
::VGPRRegBankID
)
311 return
&ValMappingsSGPR64OnlyVGPR32
[4];
313 assert(BankID
== AMDGPU
::SGPRRegBankID
);
314 return
&ValMappingsSGPR64OnlyVGPR32
[1];
318 } // End AMDGPU namespace.
319 } // End llvm namespace.