| blob | 601290812bb2e66e66e985d5917dc01316294d3a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
3 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV32I-SMALL
4 ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
5 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV32I-MEDIUM
6 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
7 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV32I-PIC
8 ; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
9 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV64I-SMALL
10 ; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
11 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV64I-MEDIUM
12 ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
13 ; RUN: -global-isel | FileCheck %s -check-prefixes=RV64I-PIC
15 define void @above_threshold(i32 signext %in, ptr %out) nounwind {
16 ; RV32I-SMALL-LABEL: above_threshold:
17 ; RV32I-SMALL: # %bb.0: # %entry
18 ; RV32I-SMALL-NEXT: li a2, 5
19 ; RV32I-SMALL-NEXT: addi a0, a0, -1
20 ; RV32I-SMALL-NEXT: bltu a2, a0, .LBB0_9
21 ; RV32I-SMALL-NEXT: # %bb.1: # %entry
22 ; RV32I-SMALL-NEXT: lui a2, %hi(.LJTI0_0)
23 ; RV32I-SMALL-NEXT: addi a2, a2, %lo(.LJTI0_0)
24 ; RV32I-SMALL-NEXT: slli a0, a0, 2
25 ; RV32I-SMALL-NEXT: add a0, a2, a0
26 ; RV32I-SMALL-NEXT: lw a0, 0(a0)
27 ; RV32I-SMALL-NEXT: jr a0
28 ; RV32I-SMALL-NEXT: .LBB0_2: # %bb1
29 ; RV32I-SMALL-NEXT: li a0, 4
30 ; RV32I-SMALL-NEXT: j .LBB0_8
31 ; RV32I-SMALL-NEXT: .LBB0_3: # %bb5
32 ; RV32I-SMALL-NEXT: li a0, 100
33 ; RV32I-SMALL-NEXT: j .LBB0_8
34 ; RV32I-SMALL-NEXT: .LBB0_4: # %bb3
35 ; RV32I-SMALL-NEXT: li a0, 2
36 ; RV32I-SMALL-NEXT: j .LBB0_8
37 ; RV32I-SMALL-NEXT: .LBB0_5: # %bb4
38 ; RV32I-SMALL-NEXT: li a0, 1
39 ; RV32I-SMALL-NEXT: j .LBB0_8
40 ; RV32I-SMALL-NEXT: .LBB0_6: # %bb2
41 ; RV32I-SMALL-NEXT: li a0, 3
42 ; RV32I-SMALL-NEXT: j .LBB0_8
43 ; RV32I-SMALL-NEXT: .LBB0_7: # %bb6
44 ; RV32I-SMALL-NEXT: li a0, 200
45 ; RV32I-SMALL-NEXT: .LBB0_8: # %exit
46 ; RV32I-SMALL-NEXT: sw a0, 0(a1)
47 ; RV32I-SMALL-NEXT: .LBB0_9: # %exit
48 ; RV32I-SMALL-NEXT: ret
49 ;
50 ; RV32I-MEDIUM-LABEL: above_threshold:
51 ; RV32I-MEDIUM: # %bb.0: # %entry
52 ; RV32I-MEDIUM-NEXT: li a2, 5
53 ; RV32I-MEDIUM-NEXT: addi a0, a0, -1
54 ; RV32I-MEDIUM-NEXT: bltu a2, a0, .LBB0_9
55 ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
56 ; RV32I-MEDIUM-NEXT: .Lpcrel_hi0:
57 ; RV32I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI0_0)
58 ; RV32I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
59 ; RV32I-MEDIUM-NEXT: slli a0, a0, 2
60 ; RV32I-MEDIUM-NEXT: add a0, a2, a0
61 ; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
62 ; RV32I-MEDIUM-NEXT: jr a0
63 ; RV32I-MEDIUM-NEXT: .LBB0_2: # %bb1
64 ; RV32I-MEDIUM-NEXT: li a0, 4
65 ; RV32I-MEDIUM-NEXT: j .LBB0_8
66 ; RV32I-MEDIUM-NEXT: .LBB0_3: # %bb5
67 ; RV32I-MEDIUM-NEXT: li a0, 100
68 ; RV32I-MEDIUM-NEXT: j .LBB0_8
69 ; RV32I-MEDIUM-NEXT: .LBB0_4: # %bb3
70 ; RV32I-MEDIUM-NEXT: li a0, 2
71 ; RV32I-MEDIUM-NEXT: j .LBB0_8
72 ; RV32I-MEDIUM-NEXT: .LBB0_5: # %bb4
73 ; RV32I-MEDIUM-NEXT: li a0, 1
74 ; RV32I-MEDIUM-NEXT: j .LBB0_8
75 ; RV32I-MEDIUM-NEXT: .LBB0_6: # %bb2
76 ; RV32I-MEDIUM-NEXT: li a0, 3
77 ; RV32I-MEDIUM-NEXT: j .LBB0_8
78 ; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb6
79 ; RV32I-MEDIUM-NEXT: li a0, 200
80 ; RV32I-MEDIUM-NEXT: .LBB0_8: # %exit
81 ; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
82 ; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
83 ; RV32I-MEDIUM-NEXT: ret
84 ;
85 ; RV32I-PIC-LABEL: above_threshold:
86 ; RV32I-PIC: # %bb.0: # %entry
87 ; RV32I-PIC-NEXT: li a2, 5
88 ; RV32I-PIC-NEXT: addi a0, a0, -1
89 ; RV32I-PIC-NEXT: bltu a2, a0, .LBB0_9
90 ; RV32I-PIC-NEXT: # %bb.1: # %entry
91 ; RV32I-PIC-NEXT: .Lpcrel_hi0:
92 ; RV32I-PIC-NEXT: auipc a2, %pcrel_hi(.LJTI0_0)
93 ; RV32I-PIC-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
94 ; RV32I-PIC-NEXT: slli a0, a0, 2
95 ; RV32I-PIC-NEXT: add a0, a2, a0
96 ; RV32I-PIC-NEXT: lw a0, 0(a0)
97 ; RV32I-PIC-NEXT: add a0, a0, a2
98 ; RV32I-PIC-NEXT: jr a0
99 ; RV32I-PIC-NEXT: .LBB0_2: # %bb1
100 ; RV32I-PIC-NEXT: li a0, 4
101 ; RV32I-PIC-NEXT: j .LBB0_8
102 ; RV32I-PIC-NEXT: .LBB0_3: # %bb5
103 ; RV32I-PIC-NEXT: li a0, 100
104 ; RV32I-PIC-NEXT: j .LBB0_8
105 ; RV32I-PIC-NEXT: .LBB0_4: # %bb3
106 ; RV32I-PIC-NEXT: li a0, 2
107 ; RV32I-PIC-NEXT: j .LBB0_8
108 ; RV32I-PIC-NEXT: .LBB0_5: # %bb4
109 ; RV32I-PIC-NEXT: li a0, 1
110 ; RV32I-PIC-NEXT: j .LBB0_8
111 ; RV32I-PIC-NEXT: .LBB0_6: # %bb2
112 ; RV32I-PIC-NEXT: li a0, 3
113 ; RV32I-PIC-NEXT: j .LBB0_8
114 ; RV32I-PIC-NEXT: .LBB0_7: # %bb6
115 ; RV32I-PIC-NEXT: li a0, 200
116 ; RV32I-PIC-NEXT: .LBB0_8: # %exit
117 ; RV32I-PIC-NEXT: sw a0, 0(a1)
118 ; RV32I-PIC-NEXT: .LBB0_9: # %exit
119 ; RV32I-PIC-NEXT: ret
120 ;
121 ; RV64I-SMALL-LABEL: above_threshold:
122 ; RV64I-SMALL: # %bb.0: # %entry
123 ; RV64I-SMALL-NEXT: li a2, 5
124 ; RV64I-SMALL-NEXT: sext.w a0, a0
125 ; RV64I-SMALL-NEXT: addi a0, a0, -1
126 ; RV64I-SMALL-NEXT: bltu a2, a0, .LBB0_9
127 ; RV64I-SMALL-NEXT: # %bb.1: # %entry
128 ; RV64I-SMALL-NEXT: lui a2, %hi(.LJTI0_0)
129 ; RV64I-SMALL-NEXT: addi a2, a2, %lo(.LJTI0_0)
130 ; RV64I-SMALL-NEXT: slli a0, a0, 2
131 ; RV64I-SMALL-NEXT: add a0, a2, a0
132 ; RV64I-SMALL-NEXT: lw a0, 0(a0)
133 ; RV64I-SMALL-NEXT: jr a0
134 ; RV64I-SMALL-NEXT: .LBB0_2: # %bb1
135 ; RV64I-SMALL-NEXT: li a0, 4
136 ; RV64I-SMALL-NEXT: j .LBB0_8
137 ; RV64I-SMALL-NEXT: .LBB0_3: # %bb5
138 ; RV64I-SMALL-NEXT: li a0, 100
139 ; RV64I-SMALL-NEXT: j .LBB0_8
140 ; RV64I-SMALL-NEXT: .LBB0_4: # %bb3
141 ; RV64I-SMALL-NEXT: li a0, 2
142 ; RV64I-SMALL-NEXT: j .LBB0_8
143 ; RV64I-SMALL-NEXT: .LBB0_5: # %bb4
144 ; RV64I-SMALL-NEXT: li a0, 1
145 ; RV64I-SMALL-NEXT: j .LBB0_8
146 ; RV64I-SMALL-NEXT: .LBB0_6: # %bb2
147 ; RV64I-SMALL-NEXT: li a0, 3
148 ; RV64I-SMALL-NEXT: j .LBB0_8
149 ; RV64I-SMALL-NEXT: .LBB0_7: # %bb6
150 ; RV64I-SMALL-NEXT: li a0, 200
151 ; RV64I-SMALL-NEXT: .LBB0_8: # %exit
152 ; RV64I-SMALL-NEXT: sw a0, 0(a1)
153 ; RV64I-SMALL-NEXT: .LBB0_9: # %exit
154 ; RV64I-SMALL-NEXT: ret
155 ;
156 ; RV64I-MEDIUM-LABEL: above_threshold:
157 ; RV64I-MEDIUM: # %bb.0: # %entry
158 ; RV64I-MEDIUM-NEXT: li a2, 5
159 ; RV64I-MEDIUM-NEXT: sext.w a0, a0
160 ; RV64I-MEDIUM-NEXT: addi a0, a0, -1
161 ; RV64I-MEDIUM-NEXT: bltu a2, a0, .LBB0_9
162 ; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
163 ; RV64I-MEDIUM-NEXT: .Lpcrel_hi0:
164 ; RV64I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI0_0)
165 ; RV64I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
166 ; RV64I-MEDIUM-NEXT: slli a0, a0, 3
167 ; RV64I-MEDIUM-NEXT: add a0, a2, a0
168 ; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
169 ; RV64I-MEDIUM-NEXT: jr a0
170 ; RV64I-MEDIUM-NEXT: .LBB0_2: # %bb1
171 ; RV64I-MEDIUM-NEXT: li a0, 4
172 ; RV64I-MEDIUM-NEXT: j .LBB0_8
173 ; RV64I-MEDIUM-NEXT: .LBB0_3: # %bb5
174 ; RV64I-MEDIUM-NEXT: li a0, 100
175 ; RV64I-MEDIUM-NEXT: j .LBB0_8
176 ; RV64I-MEDIUM-NEXT: .LBB0_4: # %bb3
177 ; RV64I-MEDIUM-NEXT: li a0, 2
178 ; RV64I-MEDIUM-NEXT: j .LBB0_8
179 ; RV64I-MEDIUM-NEXT: .LBB0_5: # %bb4
180 ; RV64I-MEDIUM-NEXT: li a0, 1
181 ; RV64I-MEDIUM-NEXT: j .LBB0_8
182 ; RV64I-MEDIUM-NEXT: .LBB0_6: # %bb2
183 ; RV64I-MEDIUM-NEXT: li a0, 3
184 ; RV64I-MEDIUM-NEXT: j .LBB0_8
185 ; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb6
186 ; RV64I-MEDIUM-NEXT: li a0, 200
187 ; RV64I-MEDIUM-NEXT: .LBB0_8: # %exit
188 ; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
189 ; RV64I-MEDIUM-NEXT: .LBB0_9: # %exit
190 ; RV64I-MEDIUM-NEXT: ret
191 ;
192 ; RV64I-PIC-LABEL: above_threshold:
193 ; RV64I-PIC: # %bb.0: # %entry
194 ; RV64I-PIC-NEXT: li a2, 5
195 ; RV64I-PIC-NEXT: sext.w a0, a0
196 ; RV64I-PIC-NEXT: addi a0, a0, -1
197 ; RV64I-PIC-NEXT: bltu a2, a0, .LBB0_9
198 ; RV64I-PIC-NEXT: # %bb.1: # %entry
199 ; RV64I-PIC-NEXT: .Lpcrel_hi0:
200 ; RV64I-PIC-NEXT: auipc a2, %pcrel_hi(.LJTI0_0)
201 ; RV64I-PIC-NEXT: addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
202 ; RV64I-PIC-NEXT: slli a0, a0, 2
203 ; RV64I-PIC-NEXT: add a0, a2, a0
204 ; RV64I-PIC-NEXT: lw a0, 0(a0)
205 ; RV64I-PIC-NEXT: add a0, a0, a2
206 ; RV64I-PIC-NEXT: jr a0
207 ; RV64I-PIC-NEXT: .LBB0_2: # %bb1
208 ; RV64I-PIC-NEXT: li a0, 4
209 ; RV64I-PIC-NEXT: j .LBB0_8
210 ; RV64I-PIC-NEXT: .LBB0_3: # %bb5
211 ; RV64I-PIC-NEXT: li a0, 100
212 ; RV64I-PIC-NEXT: j .LBB0_8
213 ; RV64I-PIC-NEXT: .LBB0_4: # %bb3
214 ; RV64I-PIC-NEXT: li a0, 2
215 ; RV64I-PIC-NEXT: j .LBB0_8
216 ; RV64I-PIC-NEXT: .LBB0_5: # %bb4
217 ; RV64I-PIC-NEXT: li a0, 1
218 ; RV64I-PIC-NEXT: j .LBB0_8
219 ; RV64I-PIC-NEXT: .LBB0_6: # %bb2
220 ; RV64I-PIC-NEXT: li a0, 3
221 ; RV64I-PIC-NEXT: j .LBB0_8
222 ; RV64I-PIC-NEXT: .LBB0_7: # %bb6
223 ; RV64I-PIC-NEXT: li a0, 200
224 ; RV64I-PIC-NEXT: .LBB0_8: # %exit
225 ; RV64I-PIC-NEXT: sw a0, 0(a1)
226 ; RV64I-PIC-NEXT: .LBB0_9: # %exit
227 ; RV64I-PIC-NEXT: ret
228 entry:
229 switch i32 %in, label %exit [
230 i32 1, label %bb1
231 i32 2, label %bb2
232 i32 3, label %bb3
233 i32 4, label %bb4
234 i32 5, label %bb5
235 i32 6, label %bb6
236 ]
237 bb1:
238 store i32 4, ptr %out
239 br label %exit
240 bb2:
241 store i32 3, ptr %out
242 br label %exit
243 bb3:
244 store i32 2, ptr %out
245 br label %exit
246 bb4:
247 store i32 1, ptr %out
248 br label %exit
249 bb5:
250 store i32 100, ptr %out
251 br label %exit
252 bb6:
253 store i32 200, ptr %out
254 br label %exit
255 exit:
256 ret void
257 }