1 ; RUN: llc -mtriple=riscv32 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
2 ; RUN: grep -v "Verify generated machine code" | \
3 ; RUN: FileCheck %s --check-prefixes=CHECK
4 ; RUN: llc -mtriple=riscv64 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
5 ; RUN: grep -v "Verify generated machine code" | \
6 ; RUN: FileCheck %s --check-prefixes=CHECK
10 ; CHECK-LABEL: Pass Arguments:
11 ; CHECK-NEXT: Target Library Information
12 ; CHECK-NEXT: Target Pass Configuration
13 ; CHECK-NEXT: Machine Module Information
14 ; CHECK-NEXT: Target Transform Information
15 ; CHECK-NEXT: Create Garbage Collector Module Metadata
16 ; CHECK-NEXT: Assumption Cache Tracker
17 ; CHECK-NEXT: Profile summary info
18 ; CHECK-NEXT: Machine Branch Probability Analysis
19 ; CHECK-NEXT: ModulePass Manager
20 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
21 ; CHECK-NEXT: FunctionPass Manager
22 ; CHECK-NEXT: Expand large div/rem
23 ; CHECK-NEXT: Expand large fp convert
24 ; CHECK-NEXT: Expand Atomic instructions
25 ; CHECK-NEXT: Module Verifier
26 ; CHECK-NEXT: Lower Garbage Collection Instructions
27 ; CHECK-NEXT: Shadow Stack GC Lowering
28 ; CHECK-NEXT: Lower constant intrinsics
29 ; CHECK-NEXT: Remove unreachable blocks from the CFG
30 ; CHECK-NEXT: Expand vector predication intrinsics
31 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
32 ; CHECK-NEXT: Expand reduction intrinsics
33 ; CHECK-NEXT: Exception handling preparation
34 ; CHECK-NEXT: Prepare callbr
35 ; CHECK-NEXT: Safe Stack instrumentation pass
36 ; CHECK-NEXT: Insert stack protectors
37 ; CHECK-NEXT: Module Verifier
38 ; CHECK-NEXT: Assignment Tracking Analysis
39 ; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
40 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
41 ; CHECK-NEXT: Local Stack Slot Allocation
42 ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
43 ; CHECK-NEXT: RISC-V Insert VSETVLI pass
44 ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
45 ; CHECK-NEXT: RISC-V Insert Write VXRM Pass
46 ; CHECK-NEXT: RISC-V init undef pass
47 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
48 ; CHECK-NEXT: Two-Address instruction pass
49 ; CHECK-NEXT: Fast Register Allocator
50 ; CHECK-NEXT: Fast Register Allocator
51 ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
52 ; CHECK-NEXT: Fixup Statepoint Caller Saved
53 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
54 ; CHECK-NEXT: Machine Optimization Remark Emitter
55 ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
56 ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
57 ; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
58 ; CHECK-NEXT: Insert KCFI indirect call checks
59 ; CHECK-NEXT: Analyze Machine Code For Garbage Collection
60 ; CHECK-NEXT: Insert fentry calls
61 ; CHECK-NEXT: Insert XRay ops
62 ; CHECK-NEXT: Implement the 'patchable-function' attribute
63 ; CHECK-NEXT: Branch relaxation pass
64 ; CHECK-NEXT: RISC-V Make Compressible
65 ; CHECK-NEXT: Contiguously Lay Out Funclets
66 ; CHECK-NEXT: StackMap Liveness Analysis
67 ; CHECK-NEXT: Live DEBUG_VALUE analysis
68 ; CHECK-NEXT: Machine Sanitizer Binary Metadata
69 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
70 ; CHECK-NEXT: Machine Optimization Remark Emitter
71 ; CHECK-NEXT: Stack Frame Layout Analysis
72 ; CHECK-NEXT: RISC-V pseudo instruction expansion pass
73 ; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
74 ; CHECK-NEXT: Unpack machine instruction bundles
75 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
76 ; CHECK-NEXT: Machine Optimization Remark Emitter
77 ; CHECK-NEXT: RISC-V Assembly Printer
78 ; CHECK-NEXT: Free MachineFunction