| blob | d864ff51b4669b6506af842b728b6c84d47abf00 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
4 ; RUN: -target-abi=ilp32d | FileCheck %s
5 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
6 ; RUN: -target-abi=lp64d | FileCheck %s
7 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
8 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32ZDINX %s
9 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
10 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64ZDINX %s
12 define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double %d) {
13 ; CHECK-LABEL: select_icmp_eq:
14 ; CHECK: # %bb.0:
15 ; CHECK-NEXT: beq a0, a1, .LBB0_2
16 ; CHECK-NEXT: # %bb.1:
17 ; CHECK-NEXT: fmv.d fa0, fa1
18 ; CHECK-NEXT: .LBB0_2:
19 ; CHECK-NEXT: ret
20 ;
21 ; RV32ZDINX-LABEL: select_icmp_eq:
22 ; RV32ZDINX: # %bb.0:
23 ; RV32ZDINX-NEXT: addi sp, sp, -16
24 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
25 ; RV32ZDINX-NEXT: sw a4, 8(sp)
26 ; RV32ZDINX-NEXT: sw a5, 12(sp)
27 ; RV32ZDINX-NEXT: lw a4, 8(sp)
28 ; RV32ZDINX-NEXT: lw a5, 12(sp)
29 ; RV32ZDINX-NEXT: sw a2, 8(sp)
30 ; RV32ZDINX-NEXT: sw a3, 12(sp)
31 ; RV32ZDINX-NEXT: bne a0, a1, .LBB0_2
32 ; RV32ZDINX-NEXT: # %bb.1:
33 ; RV32ZDINX-NEXT: lw a4, 8(sp)
34 ; RV32ZDINX-NEXT: lw a5, 12(sp)
35 ; RV32ZDINX-NEXT: .LBB0_2:
36 ; RV32ZDINX-NEXT: sw a4, 8(sp)
37 ; RV32ZDINX-NEXT: sw a5, 12(sp)
38 ; RV32ZDINX-NEXT: lw a0, 8(sp)
39 ; RV32ZDINX-NEXT: lw a1, 12(sp)
40 ; RV32ZDINX-NEXT: addi sp, sp, 16
41 ; RV32ZDINX-NEXT: ret
42 ;
43 ; RV64ZDINX-LABEL: select_icmp_eq:
44 ; RV64ZDINX: # %bb.0:
45 ; RV64ZDINX-NEXT: beq a0, a1, .LBB0_2
46 ; RV64ZDINX-NEXT: # %bb.1:
47 ; RV64ZDINX-NEXT: mv a2, a3
48 ; RV64ZDINX-NEXT: .LBB0_2:
49 ; RV64ZDINX-NEXT: mv a0, a2
50 ; RV64ZDINX-NEXT: ret
51 %1 = icmp eq i32 %a, %b
52 %2 = select i1 %1, double %c, double %d
53 ret double %2
54 }
56 define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double %d) {
57 ; CHECK-LABEL: select_icmp_ne:
58 ; CHECK: # %bb.0:
59 ; CHECK-NEXT: bne a0, a1, .LBB1_2
60 ; CHECK-NEXT: # %bb.1:
61 ; CHECK-NEXT: fmv.d fa0, fa1
62 ; CHECK-NEXT: .LBB1_2:
63 ; CHECK-NEXT: ret
64 ;
65 ; RV32ZDINX-LABEL: select_icmp_ne:
66 ; RV32ZDINX: # %bb.0:
67 ; RV32ZDINX-NEXT: addi sp, sp, -16
68 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
69 ; RV32ZDINX-NEXT: sw a4, 8(sp)
70 ; RV32ZDINX-NEXT: sw a5, 12(sp)
71 ; RV32ZDINX-NEXT: lw a4, 8(sp)
72 ; RV32ZDINX-NEXT: lw a5, 12(sp)
73 ; RV32ZDINX-NEXT: sw a2, 8(sp)
74 ; RV32ZDINX-NEXT: sw a3, 12(sp)
75 ; RV32ZDINX-NEXT: beq a0, a1, .LBB1_2
76 ; RV32ZDINX-NEXT: # %bb.1:
77 ; RV32ZDINX-NEXT: lw a4, 8(sp)
78 ; RV32ZDINX-NEXT: lw a5, 12(sp)
79 ; RV32ZDINX-NEXT: .LBB1_2:
80 ; RV32ZDINX-NEXT: sw a4, 8(sp)
81 ; RV32ZDINX-NEXT: sw a5, 12(sp)
82 ; RV32ZDINX-NEXT: lw a0, 8(sp)
83 ; RV32ZDINX-NEXT: lw a1, 12(sp)
84 ; RV32ZDINX-NEXT: addi sp, sp, 16
85 ; RV32ZDINX-NEXT: ret
86 ;
87 ; RV64ZDINX-LABEL: select_icmp_ne:
88 ; RV64ZDINX: # %bb.0:
89 ; RV64ZDINX-NEXT: bne a0, a1, .LBB1_2
90 ; RV64ZDINX-NEXT: # %bb.1:
91 ; RV64ZDINX-NEXT: mv a2, a3
92 ; RV64ZDINX-NEXT: .LBB1_2:
93 ; RV64ZDINX-NEXT: mv a0, a2
94 ; RV64ZDINX-NEXT: ret
95 %1 = icmp ne i32 %a, %b
96 %2 = select i1 %1, double %c, double %d
97 ret double %2
98 }
100 define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double %d) {
101 ; CHECK-LABEL: select_icmp_ugt:
102 ; CHECK: # %bb.0:
103 ; CHECK-NEXT: bltu a1, a0, .LBB2_2
104 ; CHECK-NEXT: # %bb.1:
105 ; CHECK-NEXT: fmv.d fa0, fa1
106 ; CHECK-NEXT: .LBB2_2:
107 ; CHECK-NEXT: ret
108 ;
109 ; RV32ZDINX-LABEL: select_icmp_ugt:
110 ; RV32ZDINX: # %bb.0:
111 ; RV32ZDINX-NEXT: addi sp, sp, -16
112 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
113 ; RV32ZDINX-NEXT: sw a4, 8(sp)
114 ; RV32ZDINX-NEXT: sw a5, 12(sp)
115 ; RV32ZDINX-NEXT: lw a4, 8(sp)
116 ; RV32ZDINX-NEXT: lw a5, 12(sp)
117 ; RV32ZDINX-NEXT: sw a2, 8(sp)
118 ; RV32ZDINX-NEXT: sw a3, 12(sp)
119 ; RV32ZDINX-NEXT: bgeu a1, a0, .LBB2_2
120 ; RV32ZDINX-NEXT: # %bb.1:
121 ; RV32ZDINX-NEXT: lw a4, 8(sp)
122 ; RV32ZDINX-NEXT: lw a5, 12(sp)
123 ; RV32ZDINX-NEXT: .LBB2_2:
124 ; RV32ZDINX-NEXT: sw a4, 8(sp)
125 ; RV32ZDINX-NEXT: sw a5, 12(sp)
126 ; RV32ZDINX-NEXT: lw a0, 8(sp)
127 ; RV32ZDINX-NEXT: lw a1, 12(sp)
128 ; RV32ZDINX-NEXT: addi sp, sp, 16
129 ; RV32ZDINX-NEXT: ret
130 ;
131 ; RV64ZDINX-LABEL: select_icmp_ugt:
132 ; RV64ZDINX: # %bb.0:
133 ; RV64ZDINX-NEXT: bltu a1, a0, .LBB2_2
134 ; RV64ZDINX-NEXT: # %bb.1:
135 ; RV64ZDINX-NEXT: mv a2, a3
136 ; RV64ZDINX-NEXT: .LBB2_2:
137 ; RV64ZDINX-NEXT: mv a0, a2
138 ; RV64ZDINX-NEXT: ret
139 %1 = icmp ugt i32 %a, %b
140 %2 = select i1 %1, double %c, double %d
141 ret double %2
142 }
144 define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double %d) {
145 ; CHECK-LABEL: select_icmp_uge:
146 ; CHECK: # %bb.0:
147 ; CHECK-NEXT: bgeu a0, a1, .LBB3_2
148 ; CHECK-NEXT: # %bb.1:
149 ; CHECK-NEXT: fmv.d fa0, fa1
150 ; CHECK-NEXT: .LBB3_2:
151 ; CHECK-NEXT: ret
152 ;
153 ; RV32ZDINX-LABEL: select_icmp_uge:
154 ; RV32ZDINX: # %bb.0:
155 ; RV32ZDINX-NEXT: addi sp, sp, -16
156 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
157 ; RV32ZDINX-NEXT: sw a4, 8(sp)
158 ; RV32ZDINX-NEXT: sw a5, 12(sp)
159 ; RV32ZDINX-NEXT: lw a4, 8(sp)
160 ; RV32ZDINX-NEXT: lw a5, 12(sp)
161 ; RV32ZDINX-NEXT: sw a2, 8(sp)
162 ; RV32ZDINX-NEXT: sw a3, 12(sp)
163 ; RV32ZDINX-NEXT: bltu a0, a1, .LBB3_2
164 ; RV32ZDINX-NEXT: # %bb.1:
165 ; RV32ZDINX-NEXT: lw a4, 8(sp)
166 ; RV32ZDINX-NEXT: lw a5, 12(sp)
167 ; RV32ZDINX-NEXT: .LBB3_2:
168 ; RV32ZDINX-NEXT: sw a4, 8(sp)
169 ; RV32ZDINX-NEXT: sw a5, 12(sp)
170 ; RV32ZDINX-NEXT: lw a0, 8(sp)
171 ; RV32ZDINX-NEXT: lw a1, 12(sp)
172 ; RV32ZDINX-NEXT: addi sp, sp, 16
173 ; RV32ZDINX-NEXT: ret
174 ;
175 ; RV64ZDINX-LABEL: select_icmp_uge:
176 ; RV64ZDINX: # %bb.0:
177 ; RV64ZDINX-NEXT: bgeu a0, a1, .LBB3_2
178 ; RV64ZDINX-NEXT: # %bb.1:
179 ; RV64ZDINX-NEXT: mv a2, a3
180 ; RV64ZDINX-NEXT: .LBB3_2:
181 ; RV64ZDINX-NEXT: mv a0, a2
182 ; RV64ZDINX-NEXT: ret
183 %1 = icmp uge i32 %a, %b
184 %2 = select i1 %1, double %c, double %d
185 ret double %2
186 }
188 define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double %d) {
189 ; CHECK-LABEL: select_icmp_ult:
190 ; CHECK: # %bb.0:
191 ; CHECK-NEXT: bltu a0, a1, .LBB4_2
192 ; CHECK-NEXT: # %bb.1:
193 ; CHECK-NEXT: fmv.d fa0, fa1
194 ; CHECK-NEXT: .LBB4_2:
195 ; CHECK-NEXT: ret
196 ;
197 ; RV32ZDINX-LABEL: select_icmp_ult:
198 ; RV32ZDINX: # %bb.0:
199 ; RV32ZDINX-NEXT: addi sp, sp, -16
200 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
201 ; RV32ZDINX-NEXT: sw a4, 8(sp)
202 ; RV32ZDINX-NEXT: sw a5, 12(sp)
203 ; RV32ZDINX-NEXT: lw a4, 8(sp)
204 ; RV32ZDINX-NEXT: lw a5, 12(sp)
205 ; RV32ZDINX-NEXT: sw a2, 8(sp)
206 ; RV32ZDINX-NEXT: sw a3, 12(sp)
207 ; RV32ZDINX-NEXT: bgeu a0, a1, .LBB4_2
208 ; RV32ZDINX-NEXT: # %bb.1:
209 ; RV32ZDINX-NEXT: lw a4, 8(sp)
210 ; RV32ZDINX-NEXT: lw a5, 12(sp)
211 ; RV32ZDINX-NEXT: .LBB4_2:
212 ; RV32ZDINX-NEXT: sw a4, 8(sp)
213 ; RV32ZDINX-NEXT: sw a5, 12(sp)
214 ; RV32ZDINX-NEXT: lw a0, 8(sp)
215 ; RV32ZDINX-NEXT: lw a1, 12(sp)
216 ; RV32ZDINX-NEXT: addi sp, sp, 16
217 ; RV32ZDINX-NEXT: ret
218 ;
219 ; RV64ZDINX-LABEL: select_icmp_ult:
220 ; RV64ZDINX: # %bb.0:
221 ; RV64ZDINX-NEXT: bltu a0, a1, .LBB4_2
222 ; RV64ZDINX-NEXT: # %bb.1:
223 ; RV64ZDINX-NEXT: mv a2, a3
224 ; RV64ZDINX-NEXT: .LBB4_2:
225 ; RV64ZDINX-NEXT: mv a0, a2
226 ; RV64ZDINX-NEXT: ret
227 %1 = icmp ult i32 %a, %b
228 %2 = select i1 %1, double %c, double %d
229 ret double %2
230 }
232 define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double %d) {
233 ; CHECK-LABEL: select_icmp_ule:
234 ; CHECK: # %bb.0:
235 ; CHECK-NEXT: bgeu a1, a0, .LBB5_2
236 ; CHECK-NEXT: # %bb.1:
237 ; CHECK-NEXT: fmv.d fa0, fa1
238 ; CHECK-NEXT: .LBB5_2:
239 ; CHECK-NEXT: ret
240 ;
241 ; RV32ZDINX-LABEL: select_icmp_ule:
242 ; RV32ZDINX: # %bb.0:
243 ; RV32ZDINX-NEXT: addi sp, sp, -16
244 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
245 ; RV32ZDINX-NEXT: sw a4, 8(sp)
246 ; RV32ZDINX-NEXT: sw a5, 12(sp)
247 ; RV32ZDINX-NEXT: lw a4, 8(sp)
248 ; RV32ZDINX-NEXT: lw a5, 12(sp)
249 ; RV32ZDINX-NEXT: sw a2, 8(sp)
250 ; RV32ZDINX-NEXT: sw a3, 12(sp)
251 ; RV32ZDINX-NEXT: bltu a1, a0, .LBB5_2
252 ; RV32ZDINX-NEXT: # %bb.1:
253 ; RV32ZDINX-NEXT: lw a4, 8(sp)
254 ; RV32ZDINX-NEXT: lw a5, 12(sp)
255 ; RV32ZDINX-NEXT: .LBB5_2:
256 ; RV32ZDINX-NEXT: sw a4, 8(sp)
257 ; RV32ZDINX-NEXT: sw a5, 12(sp)
258 ; RV32ZDINX-NEXT: lw a0, 8(sp)
259 ; RV32ZDINX-NEXT: lw a1, 12(sp)
260 ; RV32ZDINX-NEXT: addi sp, sp, 16
261 ; RV32ZDINX-NEXT: ret
262 ;
263 ; RV64ZDINX-LABEL: select_icmp_ule:
264 ; RV64ZDINX: # %bb.0:
265 ; RV64ZDINX-NEXT: bgeu a1, a0, .LBB5_2
266 ; RV64ZDINX-NEXT: # %bb.1:
267 ; RV64ZDINX-NEXT: mv a2, a3
268 ; RV64ZDINX-NEXT: .LBB5_2:
269 ; RV64ZDINX-NEXT: mv a0, a2
270 ; RV64ZDINX-NEXT: ret
271 %1 = icmp ule i32 %a, %b
272 %2 = select i1 %1, double %c, double %d
273 ret double %2
274 }
276 define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double %d) {
277 ; CHECK-LABEL: select_icmp_sgt:
278 ; CHECK: # %bb.0:
279 ; CHECK-NEXT: blt a1, a0, .LBB6_2
280 ; CHECK-NEXT: # %bb.1:
281 ; CHECK-NEXT: fmv.d fa0, fa1
282 ; CHECK-NEXT: .LBB6_2:
283 ; CHECK-NEXT: ret
284 ;
285 ; RV32ZDINX-LABEL: select_icmp_sgt:
286 ; RV32ZDINX: # %bb.0:
287 ; RV32ZDINX-NEXT: addi sp, sp, -16
288 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
289 ; RV32ZDINX-NEXT: sw a4, 8(sp)
290 ; RV32ZDINX-NEXT: sw a5, 12(sp)
291 ; RV32ZDINX-NEXT: lw a4, 8(sp)
292 ; RV32ZDINX-NEXT: lw a5, 12(sp)
293 ; RV32ZDINX-NEXT: sw a2, 8(sp)
294 ; RV32ZDINX-NEXT: sw a3, 12(sp)
295 ; RV32ZDINX-NEXT: bge a1, a0, .LBB6_2
296 ; RV32ZDINX-NEXT: # %bb.1:
297 ; RV32ZDINX-NEXT: lw a4, 8(sp)
298 ; RV32ZDINX-NEXT: lw a5, 12(sp)
299 ; RV32ZDINX-NEXT: .LBB6_2:
300 ; RV32ZDINX-NEXT: sw a4, 8(sp)
301 ; RV32ZDINX-NEXT: sw a5, 12(sp)
302 ; RV32ZDINX-NEXT: lw a0, 8(sp)
303 ; RV32ZDINX-NEXT: lw a1, 12(sp)
304 ; RV32ZDINX-NEXT: addi sp, sp, 16
305 ; RV32ZDINX-NEXT: ret
306 ;
307 ; RV64ZDINX-LABEL: select_icmp_sgt:
308 ; RV64ZDINX: # %bb.0:
309 ; RV64ZDINX-NEXT: blt a1, a0, .LBB6_2
310 ; RV64ZDINX-NEXT: # %bb.1:
311 ; RV64ZDINX-NEXT: mv a2, a3
312 ; RV64ZDINX-NEXT: .LBB6_2:
313 ; RV64ZDINX-NEXT: mv a0, a2
314 ; RV64ZDINX-NEXT: ret
315 %1 = icmp sgt i32 %a, %b
316 %2 = select i1 %1, double %c, double %d
317 ret double %2
318 }
320 define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double %d) {
321 ; CHECK-LABEL: select_icmp_sge:
322 ; CHECK: # %bb.0:
323 ; CHECK-NEXT: bge a0, a1, .LBB7_2
324 ; CHECK-NEXT: # %bb.1:
325 ; CHECK-NEXT: fmv.d fa0, fa1
326 ; CHECK-NEXT: .LBB7_2:
327 ; CHECK-NEXT: ret
328 ;
329 ; RV32ZDINX-LABEL: select_icmp_sge:
330 ; RV32ZDINX: # %bb.0:
331 ; RV32ZDINX-NEXT: addi sp, sp, -16
332 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
333 ; RV32ZDINX-NEXT: sw a4, 8(sp)
334 ; RV32ZDINX-NEXT: sw a5, 12(sp)
335 ; RV32ZDINX-NEXT: lw a4, 8(sp)
336 ; RV32ZDINX-NEXT: lw a5, 12(sp)
337 ; RV32ZDINX-NEXT: sw a2, 8(sp)
338 ; RV32ZDINX-NEXT: sw a3, 12(sp)
339 ; RV32ZDINX-NEXT: blt a0, a1, .LBB7_2
340 ; RV32ZDINX-NEXT: # %bb.1:
341 ; RV32ZDINX-NEXT: lw a4, 8(sp)
342 ; RV32ZDINX-NEXT: lw a5, 12(sp)
343 ; RV32ZDINX-NEXT: .LBB7_2:
344 ; RV32ZDINX-NEXT: sw a4, 8(sp)
345 ; RV32ZDINX-NEXT: sw a5, 12(sp)
346 ; RV32ZDINX-NEXT: lw a0, 8(sp)
347 ; RV32ZDINX-NEXT: lw a1, 12(sp)
348 ; RV32ZDINX-NEXT: addi sp, sp, 16
349 ; RV32ZDINX-NEXT: ret
350 ;
351 ; RV64ZDINX-LABEL: select_icmp_sge:
352 ; RV64ZDINX: # %bb.0:
353 ; RV64ZDINX-NEXT: bge a0, a1, .LBB7_2
354 ; RV64ZDINX-NEXT: # %bb.1:
355 ; RV64ZDINX-NEXT: mv a2, a3
356 ; RV64ZDINX-NEXT: .LBB7_2:
357 ; RV64ZDINX-NEXT: mv a0, a2
358 ; RV64ZDINX-NEXT: ret
359 %1 = icmp sge i32 %a, %b
360 %2 = select i1 %1, double %c, double %d
361 ret double %2
362 }
364 define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double %d) {
365 ; CHECK-LABEL: select_icmp_slt:
366 ; CHECK: # %bb.0:
367 ; CHECK-NEXT: blt a0, a1, .LBB8_2
368 ; CHECK-NEXT: # %bb.1:
369 ; CHECK-NEXT: fmv.d fa0, fa1
370 ; CHECK-NEXT: .LBB8_2:
371 ; CHECK-NEXT: ret
372 ;
373 ; RV32ZDINX-LABEL: select_icmp_slt:
374 ; RV32ZDINX: # %bb.0:
375 ; RV32ZDINX-NEXT: addi sp, sp, -16
376 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
377 ; RV32ZDINX-NEXT: sw a4, 8(sp)
378 ; RV32ZDINX-NEXT: sw a5, 12(sp)
379 ; RV32ZDINX-NEXT: lw a4, 8(sp)
380 ; RV32ZDINX-NEXT: lw a5, 12(sp)
381 ; RV32ZDINX-NEXT: sw a2, 8(sp)
382 ; RV32ZDINX-NEXT: sw a3, 12(sp)
383 ; RV32ZDINX-NEXT: bge a0, a1, .LBB8_2
384 ; RV32ZDINX-NEXT: # %bb.1:
385 ; RV32ZDINX-NEXT: lw a4, 8(sp)
386 ; RV32ZDINX-NEXT: lw a5, 12(sp)
387 ; RV32ZDINX-NEXT: .LBB8_2:
388 ; RV32ZDINX-NEXT: sw a4, 8(sp)
389 ; RV32ZDINX-NEXT: sw a5, 12(sp)
390 ; RV32ZDINX-NEXT: lw a0, 8(sp)
391 ; RV32ZDINX-NEXT: lw a1, 12(sp)
392 ; RV32ZDINX-NEXT: addi sp, sp, 16
393 ; RV32ZDINX-NEXT: ret
394 ;
395 ; RV64ZDINX-LABEL: select_icmp_slt:
396 ; RV64ZDINX: # %bb.0:
397 ; RV64ZDINX-NEXT: blt a0, a1, .LBB8_2
398 ; RV64ZDINX-NEXT: # %bb.1:
399 ; RV64ZDINX-NEXT: mv a2, a3
400 ; RV64ZDINX-NEXT: .LBB8_2:
401 ; RV64ZDINX-NEXT: mv a0, a2
402 ; RV64ZDINX-NEXT: ret
403 %1 = icmp slt i32 %a, %b
404 %2 = select i1 %1, double %c, double %d
405 ret double %2
406 }
408 define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double %d) {
409 ; CHECK-LABEL: select_icmp_sle:
410 ; CHECK: # %bb.0:
411 ; CHECK-NEXT: bge a1, a0, .LBB9_2
412 ; CHECK-NEXT: # %bb.1:
413 ; CHECK-NEXT: fmv.d fa0, fa1
414 ; CHECK-NEXT: .LBB9_2:
415 ; CHECK-NEXT: ret
416 ;
417 ; RV32ZDINX-LABEL: select_icmp_sle:
418 ; RV32ZDINX: # %bb.0:
419 ; RV32ZDINX-NEXT: addi sp, sp, -16
420 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
421 ; RV32ZDINX-NEXT: sw a4, 8(sp)
422 ; RV32ZDINX-NEXT: sw a5, 12(sp)
423 ; RV32ZDINX-NEXT: lw a4, 8(sp)
424 ; RV32ZDINX-NEXT: lw a5, 12(sp)
425 ; RV32ZDINX-NEXT: sw a2, 8(sp)
426 ; RV32ZDINX-NEXT: sw a3, 12(sp)
427 ; RV32ZDINX-NEXT: blt a1, a0, .LBB9_2
428 ; RV32ZDINX-NEXT: # %bb.1:
429 ; RV32ZDINX-NEXT: lw a4, 8(sp)
430 ; RV32ZDINX-NEXT: lw a5, 12(sp)
431 ; RV32ZDINX-NEXT: .LBB9_2:
432 ; RV32ZDINX-NEXT: sw a4, 8(sp)
433 ; RV32ZDINX-NEXT: sw a5, 12(sp)
434 ; RV32ZDINX-NEXT: lw a0, 8(sp)
435 ; RV32ZDINX-NEXT: lw a1, 12(sp)
436 ; RV32ZDINX-NEXT: addi sp, sp, 16
437 ; RV32ZDINX-NEXT: ret
438 ;
439 ; RV64ZDINX-LABEL: select_icmp_sle:
440 ; RV64ZDINX: # %bb.0:
441 ; RV64ZDINX-NEXT: bge a1, a0, .LBB9_2
442 ; RV64ZDINX-NEXT: # %bb.1:
443 ; RV64ZDINX-NEXT: mv a2, a3
444 ; RV64ZDINX-NEXT: .LBB9_2:
445 ; RV64ZDINX-NEXT: mv a0, a2
446 ; RV64ZDINX-NEXT: ret
447 %1 = icmp sle i32 %a, %b
448 %2 = select i1 %1, double %c, double %d
449 ret double %2
450 }
452 define double @select_icmp_slt_one(i32 signext %a) {
453 ; CHECK-LABEL: select_icmp_slt_one:
454 ; CHECK: # %bb.0:
455 ; CHECK-NEXT: slti a0, a0, 1
456 ; CHECK-NEXT: fcvt.d.w fa0, a0
457 ; CHECK-NEXT: ret
458 ;
459 ; RV32ZDINX-LABEL: select_icmp_slt_one:
460 ; RV32ZDINX: # %bb.0:
461 ; RV32ZDINX-NEXT: addi sp, sp, -16
462 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
463 ; RV32ZDINX-NEXT: slti a0, a0, 1
464 ; RV32ZDINX-NEXT: fcvt.d.w a0, a0
465 ; RV32ZDINX-NEXT: sw a0, 8(sp)
466 ; RV32ZDINX-NEXT: sw a1, 12(sp)
467 ; RV32ZDINX-NEXT: lw a0, 8(sp)
468 ; RV32ZDINX-NEXT: lw a1, 12(sp)
469 ; RV32ZDINX-NEXT: addi sp, sp, 16
470 ; RV32ZDINX-NEXT: ret
471 ;
472 ; RV64ZDINX-LABEL: select_icmp_slt_one:
473 ; RV64ZDINX: # %bb.0:
474 ; RV64ZDINX-NEXT: slti a0, a0, 1
475 ; RV64ZDINX-NEXT: fcvt.d.w a0, a0
476 ; RV64ZDINX-NEXT: ret
477 %1 = icmp slt i32 %a, 1
478 %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00
479 ret double %2
480 }
482 define double @select_icmp_sgt_zero(i32 signext %a) {
483 ; CHECK-LABEL: select_icmp_sgt_zero:
484 ; CHECK: # %bb.0:
485 ; CHECK-NEXT: slti a0, a0, 1
486 ; CHECK-NEXT: fcvt.d.w fa0, a0
487 ; CHECK-NEXT: ret
488 ;
489 ; RV32ZDINX-LABEL: select_icmp_sgt_zero:
490 ; RV32ZDINX: # %bb.0:
491 ; RV32ZDINX-NEXT: addi sp, sp, -16
492 ; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
493 ; RV32ZDINX-NEXT: slti a0, a0, 1
494 ; RV32ZDINX-NEXT: fcvt.d.w a0, a0
495 ; RV32ZDINX-NEXT: sw a0, 8(sp)
496 ; RV32ZDINX-NEXT: sw a1, 12(sp)
497 ; RV32ZDINX-NEXT: lw a0, 8(sp)
498 ; RV32ZDINX-NEXT: lw a1, 12(sp)
499 ; RV32ZDINX-NEXT: addi sp, sp, 16
500 ; RV32ZDINX-NEXT: ret
501 ;
502 ; RV64ZDINX-LABEL: select_icmp_sgt_zero:
503 ; RV64ZDINX: # %bb.0:
504 ; RV64ZDINX-NEXT: slti a0, a0, 1
505 ; RV64ZDINX-NEXT: fcvt.d.w a0, a0
506 ; RV64ZDINX-NEXT: ret
507 %1 = icmp sgt i32 %a, 0
508 %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
509 ret double %2
510 }