1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32F %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV64F %s
7 @gd = external global double
9 define double @constraint_f_double(double %a) nounwind {
10 ; RV32F-LABEL: constraint_f_double:
12 ; RV32F-NEXT: addi sp, sp, -16
13 ; RV32F-NEXT: sw a0, 8(sp)
14 ; RV32F-NEXT: sw a1, 12(sp)
15 ; RV32F-NEXT: fld fa5, 8(sp)
16 ; RV32F-NEXT: lui a0, %hi(gd)
17 ; RV32F-NEXT: fld fa4, %lo(gd)(a0)
19 ; RV32F-NEXT: fadd.d fa5, fa5, fa4
21 ; RV32F-NEXT: fsd fa5, 8(sp)
22 ; RV32F-NEXT: lw a0, 8(sp)
23 ; RV32F-NEXT: lw a1, 12(sp)
24 ; RV32F-NEXT: addi sp, sp, 16
27 ; RV64F-LABEL: constraint_f_double:
29 ; RV64F-NEXT: lui a1, %hi(gd)
30 ; RV64F-NEXT: fld fa5, %lo(gd)(a1)
31 ; RV64F-NEXT: fmv.d.x fa4, a0
33 ; RV64F-NEXT: fadd.d fa5, fa4, fa5
35 ; RV64F-NEXT: fmv.x.d a0, fa5
37 %1 = load double, ptr @gd
38 %2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
42 define double @constraint_f_double_abi_name(double %a) nounwind {
43 ; RV32F-LABEL: constraint_f_double_abi_name:
45 ; RV32F-NEXT: addi sp, sp, -16
46 ; RV32F-NEXT: sw a0, 8(sp)
47 ; RV32F-NEXT: sw a1, 12(sp)
48 ; RV32F-NEXT: fld fa1, 8(sp)
49 ; RV32F-NEXT: lui a0, %hi(gd)
50 ; RV32F-NEXT: fld fs0, %lo(gd)(a0)
52 ; RV32F-NEXT: fadd.d ft0, fa1, fs0
54 ; RV32F-NEXT: fsd ft0, 8(sp)
55 ; RV32F-NEXT: lw a0, 8(sp)
56 ; RV32F-NEXT: lw a1, 12(sp)
57 ; RV32F-NEXT: addi sp, sp, 16
60 ; RV64F-LABEL: constraint_f_double_abi_name:
62 ; RV64F-NEXT: lui a1, %hi(gd)
63 ; RV64F-NEXT: fld fs0, %lo(gd)(a1)
64 ; RV64F-NEXT: fmv.d.x fa1, a0
66 ; RV64F-NEXT: fadd.d ft0, fa1, fs0
68 ; RV64F-NEXT: fmv.x.d a0, ft0
70 %1 = load double, ptr @gd
71 %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1)
75 define double @constraint_gpr(double %x) {
76 ; RV32F-LABEL: constraint_gpr:
78 ; RV32F-NEXT: addi sp, sp, -32
79 ; RV32F-NEXT: .cfi_def_cfa_offset 32
80 ; RV32F-NEXT: sw a0, 8(sp)
81 ; RV32F-NEXT: sw a1, 12(sp)
82 ; RV32F-NEXT: fld fa5, 8(sp)
83 ; RV32F-NEXT: fsd fa5, 24(sp)
84 ; RV32F-NEXT: lw a0, 24(sp)
85 ; RV32F-NEXT: lw a1, 28(sp)
87 ; RV32F-NEXT: mv a0, a0
89 ; RV32F-NEXT: sw a1, 20(sp)
90 ; RV32F-NEXT: sw a0, 16(sp)
91 ; RV32F-NEXT: fld fa5, 16(sp)
92 ; RV32F-NEXT: fsd fa5, 8(sp)
93 ; RV32F-NEXT: lw a0, 8(sp)
94 ; RV32F-NEXT: lw a1, 12(sp)
95 ; RV32F-NEXT: addi sp, sp, 32
98 ; RV64F-LABEL: constraint_gpr:
100 ; RV64F-NEXT: .cfi_def_cfa_offset 0
102 ; RV64F-NEXT: mv a0, a0
103 ; RV64F-NEXT: #NO_APP
105 %1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x)