| blob | 804bc053728d82609d58cfa6c4e6ab617f8b1697 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh \
3 ; RUN: -riscv-enable-subreg-liveness=false < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh < %s \
5 ; RUN: -riscv-enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
7 ; This testcase failed to compile after
8 ; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted.
10 ; FIXME: The failure does not reproduce with -stop-before=greedy
11 ; output MIR with -start-before=greedy
13 define void @last_chance_recoloring_failure() {
14 ; CHECK-LABEL: last_chance_recoloring_failure:
15 ; CHECK: # %bb.0: # %entry
16 ; CHECK-NEXT: addi sp, sp, -32
17 ; CHECK-NEXT: .cfi_def_cfa_offset 32
18 ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
19 ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
20 ; CHECK-NEXT: .cfi_offset ra, -8
21 ; CHECK-NEXT: .cfi_offset s0, -16
22 ; CHECK-NEXT: csrr a0, vlenb
23 ; CHECK-NEXT: slli a0, a0, 4
24 ; CHECK-NEXT: sub sp, sp, a0
25 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
26 ; CHECK-NEXT: li a0, 55
27 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
28 ; CHECK-NEXT: vloxseg2ei32.v v16, (a0), v8
29 ; CHECK-NEXT: addi a0, sp, 16
30 ; CHECK-NEXT: csrr a1, vlenb
31 ; CHECK-NEXT: slli a1, a1, 2
32 ; CHECK-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
33 ; CHECK-NEXT: add a0, a0, a1
34 ; CHECK-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill
35 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
36 ; CHECK-NEXT: vmclr.m v0
37 ; CHECK-NEXT: li s0, 36
38 ; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
39 ; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
40 ; CHECK-NEXT: csrr a0, vlenb
41 ; CHECK-NEXT: slli a0, a0, 3
42 ; CHECK-NEXT: add a0, sp, a0
43 ; CHECK-NEXT: addi a0, a0, 16
44 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
45 ; CHECK-NEXT: call func
46 ; CHECK-NEXT: li a0, 32
47 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
48 ; CHECK-NEXT: vrgather.vv v16, v8, v12, v0.t
49 ; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
50 ; CHECK-NEXT: addi a1, sp, 16
51 ; CHECK-NEXT: csrr a2, vlenb
52 ; CHECK-NEXT: slli a2, a2, 2
53 ; CHECK-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
54 ; CHECK-NEXT: add a1, a1, a2
55 ; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
56 ; CHECK-NEXT: csrr a1, vlenb
57 ; CHECK-NEXT: slli a1, a1, 3
58 ; CHECK-NEXT: add a1, sp, a1
59 ; CHECK-NEXT: addi a1, a1, 16
60 ; CHECK-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
61 ; CHECK-NEXT: vfwsub.wv v8, v0, v20
62 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
63 ; CHECK-NEXT: vssubu.vv v16, v16, v8, v0.t
64 ; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu
65 ; CHECK-NEXT: csrr a0, vlenb
66 ; CHECK-NEXT: slli a0, a0, 3
67 ; CHECK-NEXT: add a0, sp, a0
68 ; CHECK-NEXT: addi a0, a0, 16
69 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
70 ; CHECK-NEXT: vfdiv.vv v8, v16, v8, v0.t
71 ; CHECK-NEXT: vse32.v v8, (a0)
72 ; CHECK-NEXT: csrr a0, vlenb
73 ; CHECK-NEXT: slli a0, a0, 4
74 ; CHECK-NEXT: add sp, sp, a0
75 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
76 ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
77 ; CHECK-NEXT: addi sp, sp, 32
78 ; CHECK-NEXT: ret
79 ;
80 ; SUBREGLIVENESS-LABEL: last_chance_recoloring_failure:
81 ; SUBREGLIVENESS: # %bb.0: # %entry
82 ; SUBREGLIVENESS-NEXT: addi sp, sp, -32
83 ; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32
84 ; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
85 ; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
86 ; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8
87 ; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16
88 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
89 ; SUBREGLIVENESS-NEXT: slli a0, a0, 4
90 ; SUBREGLIVENESS-NEXT: sub sp, sp, a0
91 ; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
92 ; SUBREGLIVENESS-NEXT: li a0, 55
93 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
94 ; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v16, (a0), v8
95 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
96 ; SUBREGLIVENESS-NEXT: slli a0, a0, 3
97 ; SUBREGLIVENESS-NEXT: add a0, sp, a0
98 ; SUBREGLIVENESS-NEXT: addi a0, a0, 16
99 ; SUBREGLIVENESS-NEXT: csrr a1, vlenb
100 ; SUBREGLIVENESS-NEXT: slli a1, a1, 2
101 ; SUBREGLIVENESS-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
102 ; SUBREGLIVENESS-NEXT: add a0, a0, a1
103 ; SUBREGLIVENESS-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill
104 ; SUBREGLIVENESS-NEXT: vsetvli a0, zero, e8, m2, ta, ma
105 ; SUBREGLIVENESS-NEXT: vmclr.m v0
106 ; SUBREGLIVENESS-NEXT: li s0, 36
107 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
108 ; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
109 ; SUBREGLIVENESS-NEXT: addi a0, sp, 16
110 ; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
111 ; SUBREGLIVENESS-NEXT: call func
112 ; SUBREGLIVENESS-NEXT: li a0, 32
113 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
114 ; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v12, v0.t
115 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
116 ; SUBREGLIVENESS-NEXT: csrr a1, vlenb
117 ; SUBREGLIVENESS-NEXT: slli a1, a1, 3
118 ; SUBREGLIVENESS-NEXT: add a1, sp, a1
119 ; SUBREGLIVENESS-NEXT: addi a1, a1, 16
120 ; SUBREGLIVENESS-NEXT: csrr a2, vlenb
121 ; SUBREGLIVENESS-NEXT: slli a2, a2, 2
122 ; SUBREGLIVENESS-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
123 ; SUBREGLIVENESS-NEXT: add a1, a1, a2
124 ; SUBREGLIVENESS-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
125 ; SUBREGLIVENESS-NEXT: addi a1, sp, 16
126 ; SUBREGLIVENESS-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
127 ; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v20
128 ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, tu, mu
129 ; SUBREGLIVENESS-NEXT: vssubu.vv v16, v16, v8, v0.t
130 ; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e32, m8, tu, mu
131 ; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t
132 ; SUBREGLIVENESS-NEXT: vse32.v v8, (a0)
133 ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
134 ; SUBREGLIVENESS-NEXT: slli a0, a0, 4
135 ; SUBREGLIVENESS-NEXT: add sp, sp, a0
136 ; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
137 ; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
138 ; SUBREGLIVENESS-NEXT: addi sp, sp, 32
139 ; SUBREGLIVENESS-NEXT: ret
140 entry:
141 %i = call { <vscale x 16 x half>, <vscale x 16 x half>} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( <vscale x 16 x half> undef, <vscale x 16 x half> undef, ptr nonnull poison, <vscale x 16 x i32> poison, i64 55)
142 %i1 = extractvalue { <vscale x 16 x half>, <vscale x 16 x half> } %i, 0
143 %i2 = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> poison, <vscale x 16 x half> poison, <vscale x 16 x i1> zeroinitializer, i64 7, i64 36, i64 0)
144 call void @func()
145 %i3 = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)
146 %i4 = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %i2, <vscale x 16 x half> %i1, i64 7, i64 36)
147 %i5 = call <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> %i3, <vscale x 16 x i16> %i3, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0)
148 %i6 = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> %i4, <vscale x 16 x float> %i2, <vscale x 16 x float> poison, <vscale x 16 x i1> poison, i64 7, i64 36, i64 0)
149 call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %i6, <vscale x 16 x float>* nonnull poison, i64 36)
150 ret void
151 }
153 declare void @func()
154 declare { <vscale x 16 x half>, <vscale x 16 x half>} @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64( <vscale x 16 x half>, <vscale x 16 x half>, ptr nocapture, <vscale x 16 x i32>, i64)
155 declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64, i64, i64 immarg)
156 declare <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg)
157 declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x half>, i64, i64)
158 declare <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg)
159 declare <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64, i64 immarg)
160 declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64) #3