| blob | eea8e64f2dddb2398589bca8aaf7696e598fa3bc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-enable-sink-fold < %s \
3 ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
5 ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-enable-sink-fold < %s \
7 ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
9 ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
12 define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
13 ; RV32I-LABEL: fold_urem_vec_1:
14 ; RV32I: # %bb.0:
15 ; RV32I-NEXT: addi sp, sp, -32
16 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
17 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
18 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
19 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
20 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
21 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
22 ; RV32I-NEXT: lhu s0, 12(a1)
23 ; RV32I-NEXT: lhu s1, 8(a1)
24 ; RV32I-NEXT: lhu s2, 4(a1)
25 ; RV32I-NEXT: lhu a2, 0(a1)
26 ; RV32I-NEXT: mv s3, a0
27 ; RV32I-NEXT: li a1, 95
28 ; RV32I-NEXT: mv a0, a2
29 ; RV32I-NEXT: call __umodsi3
30 ; RV32I-NEXT: mv s4, a0
31 ; RV32I-NEXT: li a1, 124
32 ; RV32I-NEXT: mv a0, s2
33 ; RV32I-NEXT: call __umodsi3
34 ; RV32I-NEXT: mv s2, a0
35 ; RV32I-NEXT: li a1, 98
36 ; RV32I-NEXT: mv a0, s1
37 ; RV32I-NEXT: call __umodsi3
38 ; RV32I-NEXT: mv s1, a0
39 ; RV32I-NEXT: li a1, 1003
40 ; RV32I-NEXT: mv a0, s0
41 ; RV32I-NEXT: call __umodsi3
42 ; RV32I-NEXT: sh a0, 6(s3)
43 ; RV32I-NEXT: sh s1, 4(s3)
44 ; RV32I-NEXT: sh s2, 2(s3)
45 ; RV32I-NEXT: sh s4, 0(s3)
46 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
47 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
48 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
49 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
50 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
51 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
52 ; RV32I-NEXT: addi sp, sp, 32
53 ; RV32I-NEXT: ret
54 ;
55 ; RV32IM-LABEL: fold_urem_vec_1:
56 ; RV32IM: # %bb.0:
57 ; RV32IM-NEXT: lhu a2, 12(a1)
58 ; RV32IM-NEXT: lhu a3, 8(a1)
59 ; RV32IM-NEXT: lhu a4, 0(a1)
60 ; RV32IM-NEXT: lhu a1, 4(a1)
61 ; RV32IM-NEXT: lui a5, 11038
62 ; RV32IM-NEXT: addi a5, a5, -1465
63 ; RV32IM-NEXT: mulhu a5, a4, a5
64 ; RV32IM-NEXT: li a6, 95
65 ; RV32IM-NEXT: mul a5, a5, a6
66 ; RV32IM-NEXT: sub a4, a4, a5
67 ; RV32IM-NEXT: lui a5, 8456
68 ; RV32IM-NEXT: addi a5, a5, 1058
69 ; RV32IM-NEXT: mulhu a5, a1, a5
70 ; RV32IM-NEXT: li a6, 124
71 ; RV32IM-NEXT: mul a5, a5, a6
72 ; RV32IM-NEXT: sub a1, a1, a5
73 ; RV32IM-NEXT: lui a5, 10700
74 ; RV32IM-NEXT: addi a5, a5, -1003
75 ; RV32IM-NEXT: mulhu a5, a3, a5
76 ; RV32IM-NEXT: li a6, 98
77 ; RV32IM-NEXT: mul a5, a5, a6
78 ; RV32IM-NEXT: sub a3, a3, a5
79 ; RV32IM-NEXT: lui a5, 1045
80 ; RV32IM-NEXT: addi a5, a5, 1801
81 ; RV32IM-NEXT: mulhu a5, a2, a5
82 ; RV32IM-NEXT: li a6, 1003
83 ; RV32IM-NEXT: mul a5, a5, a6
84 ; RV32IM-NEXT: sub a2, a2, a5
85 ; RV32IM-NEXT: sh a2, 6(a0)
86 ; RV32IM-NEXT: sh a3, 4(a0)
87 ; RV32IM-NEXT: sh a1, 2(a0)
88 ; RV32IM-NEXT: sh a4, 0(a0)
89 ; RV32IM-NEXT: ret
90 ;
91 ; RV64I-LABEL: fold_urem_vec_1:
92 ; RV64I: # %bb.0:
93 ; RV64I-NEXT: addi sp, sp, -48
94 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
95 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
96 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
97 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
98 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
99 ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
100 ; RV64I-NEXT: lhu s0, 24(a1)
101 ; RV64I-NEXT: lhu s1, 16(a1)
102 ; RV64I-NEXT: lhu s2, 8(a1)
103 ; RV64I-NEXT: lhu a2, 0(a1)
104 ; RV64I-NEXT: mv s3, a0
105 ; RV64I-NEXT: li a1, 95
106 ; RV64I-NEXT: mv a0, a2
107 ; RV64I-NEXT: call __umoddi3
108 ; RV64I-NEXT: mv s4, a0
109 ; RV64I-NEXT: li a1, 124
110 ; RV64I-NEXT: mv a0, s2
111 ; RV64I-NEXT: call __umoddi3
112 ; RV64I-NEXT: mv s2, a0
113 ; RV64I-NEXT: li a1, 98
114 ; RV64I-NEXT: mv a0, s1
115 ; RV64I-NEXT: call __umoddi3
116 ; RV64I-NEXT: mv s1, a0
117 ; RV64I-NEXT: li a1, 1003
118 ; RV64I-NEXT: mv a0, s0
119 ; RV64I-NEXT: call __umoddi3
120 ; RV64I-NEXT: sh a0, 6(s3)
121 ; RV64I-NEXT: sh s1, 4(s3)
122 ; RV64I-NEXT: sh s2, 2(s3)
123 ; RV64I-NEXT: sh s4, 0(s3)
124 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
125 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
126 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
127 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
128 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
129 ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
130 ; RV64I-NEXT: addi sp, sp, 48
131 ; RV64I-NEXT: ret
132 ;
133 ; RV64IM-LABEL: fold_urem_vec_1:
134 ; RV64IM: # %bb.0:
135 ; RV64IM-NEXT: lhu a2, 0(a1)
136 ; RV64IM-NEXT: lui a3, %hi(.LCPI0_0)
137 ; RV64IM-NEXT: ld a3, %lo(.LCPI0_0)(a3)
138 ; RV64IM-NEXT: lhu a4, 24(a1)
139 ; RV64IM-NEXT: lhu a5, 16(a1)
140 ; RV64IM-NEXT: lhu a1, 8(a1)
141 ; RV64IM-NEXT: mulhu a3, a2, a3
142 ; RV64IM-NEXT: lui a6, %hi(.LCPI0_1)
143 ; RV64IM-NEXT: ld a6, %lo(.LCPI0_1)(a6)
144 ; RV64IM-NEXT: li a7, 95
145 ; RV64IM-NEXT: mul a3, a3, a7
146 ; RV64IM-NEXT: subw a2, a2, a3
147 ; RV64IM-NEXT: mulhu a3, a1, a6
148 ; RV64IM-NEXT: lui a6, %hi(.LCPI0_2)
149 ; RV64IM-NEXT: ld a6, %lo(.LCPI0_2)(a6)
150 ; RV64IM-NEXT: li a7, 124
151 ; RV64IM-NEXT: mul a3, a3, a7
152 ; RV64IM-NEXT: subw a1, a1, a3
153 ; RV64IM-NEXT: mulhu a3, a5, a6
154 ; RV64IM-NEXT: lui a6, %hi(.LCPI0_3)
155 ; RV64IM-NEXT: ld a6, %lo(.LCPI0_3)(a6)
156 ; RV64IM-NEXT: li a7, 98
157 ; RV64IM-NEXT: mul a3, a3, a7
158 ; RV64IM-NEXT: subw a5, a5, a3
159 ; RV64IM-NEXT: mulhu a3, a4, a6
160 ; RV64IM-NEXT: li a6, 1003
161 ; RV64IM-NEXT: mul a3, a3, a6
162 ; RV64IM-NEXT: subw a4, a4, a3
163 ; RV64IM-NEXT: sh a4, 6(a0)
164 ; RV64IM-NEXT: sh a5, 4(a0)
165 ; RV64IM-NEXT: sh a1, 2(a0)
166 ; RV64IM-NEXT: sh a2, 0(a0)
167 ; RV64IM-NEXT: ret
168 %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
169 ret <4 x i16> %1
170 }
172 define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
173 ; RV32I-LABEL: fold_urem_vec_2:
174 ; RV32I: # %bb.0:
175 ; RV32I-NEXT: addi sp, sp, -32
176 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
177 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
178 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
179 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
180 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
181 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
182 ; RV32I-NEXT: lhu s0, 12(a1)
183 ; RV32I-NEXT: lhu s1, 8(a1)
184 ; RV32I-NEXT: lhu s2, 4(a1)
185 ; RV32I-NEXT: lhu a2, 0(a1)
186 ; RV32I-NEXT: mv s3, a0
187 ; RV32I-NEXT: li a1, 95
188 ; RV32I-NEXT: mv a0, a2
189 ; RV32I-NEXT: call __umodsi3
190 ; RV32I-NEXT: mv s4, a0
191 ; RV32I-NEXT: li a1, 95
192 ; RV32I-NEXT: mv a0, s2
193 ; RV32I-NEXT: call __umodsi3
194 ; RV32I-NEXT: mv s2, a0
195 ; RV32I-NEXT: li a1, 95
196 ; RV32I-NEXT: mv a0, s1
197 ; RV32I-NEXT: call __umodsi3
198 ; RV32I-NEXT: mv s1, a0
199 ; RV32I-NEXT: li a1, 95
200 ; RV32I-NEXT: mv a0, s0
201 ; RV32I-NEXT: call __umodsi3
202 ; RV32I-NEXT: sh a0, 6(s3)
203 ; RV32I-NEXT: sh s1, 4(s3)
204 ; RV32I-NEXT: sh s2, 2(s3)
205 ; RV32I-NEXT: sh s4, 0(s3)
206 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
207 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
208 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
209 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
210 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
211 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
212 ; RV32I-NEXT: addi sp, sp, 32
213 ; RV32I-NEXT: ret
214 ;
215 ; RV32IM-LABEL: fold_urem_vec_2:
216 ; RV32IM: # %bb.0:
217 ; RV32IM-NEXT: lhu a2, 12(a1)
218 ; RV32IM-NEXT: lhu a3, 8(a1)
219 ; RV32IM-NEXT: lhu a4, 0(a1)
220 ; RV32IM-NEXT: lhu a1, 4(a1)
221 ; RV32IM-NEXT: lui a5, 11038
222 ; RV32IM-NEXT: addi a5, a5, -1465
223 ; RV32IM-NEXT: mulhu a6, a4, a5
224 ; RV32IM-NEXT: li a7, 95
225 ; RV32IM-NEXT: mul a6, a6, a7
226 ; RV32IM-NEXT: sub a4, a4, a6
227 ; RV32IM-NEXT: mulhu a6, a1, a5
228 ; RV32IM-NEXT: mul a6, a6, a7
229 ; RV32IM-NEXT: sub a1, a1, a6
230 ; RV32IM-NEXT: mulhu a6, a3, a5
231 ; RV32IM-NEXT: mul a6, a6, a7
232 ; RV32IM-NEXT: sub a3, a3, a6
233 ; RV32IM-NEXT: mulhu a5, a2, a5
234 ; RV32IM-NEXT: mul a5, a5, a7
235 ; RV32IM-NEXT: sub a2, a2, a5
236 ; RV32IM-NEXT: sh a2, 6(a0)
237 ; RV32IM-NEXT: sh a3, 4(a0)
238 ; RV32IM-NEXT: sh a1, 2(a0)
239 ; RV32IM-NEXT: sh a4, 0(a0)
240 ; RV32IM-NEXT: ret
241 ;
242 ; RV64I-LABEL: fold_urem_vec_2:
243 ; RV64I: # %bb.0:
244 ; RV64I-NEXT: addi sp, sp, -48
245 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
246 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
247 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
248 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
249 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
250 ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
251 ; RV64I-NEXT: lhu s0, 24(a1)
252 ; RV64I-NEXT: lhu s1, 16(a1)
253 ; RV64I-NEXT: lhu s2, 8(a1)
254 ; RV64I-NEXT: lhu a2, 0(a1)
255 ; RV64I-NEXT: mv s3, a0
256 ; RV64I-NEXT: li a1, 95
257 ; RV64I-NEXT: mv a0, a2
258 ; RV64I-NEXT: call __umoddi3
259 ; RV64I-NEXT: mv s4, a0
260 ; RV64I-NEXT: li a1, 95
261 ; RV64I-NEXT: mv a0, s2
262 ; RV64I-NEXT: call __umoddi3
263 ; RV64I-NEXT: mv s2, a0
264 ; RV64I-NEXT: li a1, 95
265 ; RV64I-NEXT: mv a0, s1
266 ; RV64I-NEXT: call __umoddi3
267 ; RV64I-NEXT: mv s1, a0
268 ; RV64I-NEXT: li a1, 95
269 ; RV64I-NEXT: mv a0, s0
270 ; RV64I-NEXT: call __umoddi3
271 ; RV64I-NEXT: sh a0, 6(s3)
272 ; RV64I-NEXT: sh s1, 4(s3)
273 ; RV64I-NEXT: sh s2, 2(s3)
274 ; RV64I-NEXT: sh s4, 0(s3)
275 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
276 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
277 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
278 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
279 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
280 ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
281 ; RV64I-NEXT: addi sp, sp, 48
282 ; RV64I-NEXT: ret
283 ;
284 ; RV64IM-LABEL: fold_urem_vec_2:
285 ; RV64IM: # %bb.0:
286 ; RV64IM-NEXT: lhu a2, 0(a1)
287 ; RV64IM-NEXT: lui a3, %hi(.LCPI1_0)
288 ; RV64IM-NEXT: ld a3, %lo(.LCPI1_0)(a3)
289 ; RV64IM-NEXT: lhu a4, 24(a1)
290 ; RV64IM-NEXT: lhu a5, 16(a1)
291 ; RV64IM-NEXT: lhu a1, 8(a1)
292 ; RV64IM-NEXT: mulhu a6, a2, a3
293 ; RV64IM-NEXT: li a7, 95
294 ; RV64IM-NEXT: mul a6, a6, a7
295 ; RV64IM-NEXT: subw a2, a2, a6
296 ; RV64IM-NEXT: mulhu a6, a1, a3
297 ; RV64IM-NEXT: mul a6, a6, a7
298 ; RV64IM-NEXT: subw a1, a1, a6
299 ; RV64IM-NEXT: mulhu a6, a5, a3
300 ; RV64IM-NEXT: mul a6, a6, a7
301 ; RV64IM-NEXT: subw a5, a5, a6
302 ; RV64IM-NEXT: mulhu a3, a4, a3
303 ; RV64IM-NEXT: mul a3, a3, a7
304 ; RV64IM-NEXT: subw a4, a4, a3
305 ; RV64IM-NEXT: sh a4, 6(a0)
306 ; RV64IM-NEXT: sh a5, 4(a0)
307 ; RV64IM-NEXT: sh a1, 2(a0)
308 ; RV64IM-NEXT: sh a2, 0(a0)
309 ; RV64IM-NEXT: ret
310 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
311 ret <4 x i16> %1
312 }
315 ; Don't fold if we can combine urem with udiv.
316 define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
317 ; RV32I-LABEL: combine_urem_udiv:
318 ; RV32I: # %bb.0:
319 ; RV32I-NEXT: addi sp, sp, -48
320 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
321 ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
322 ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
323 ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
324 ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
325 ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
326 ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
327 ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
328 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
329 ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
330 ; RV32I-NEXT: lhu s1, 0(a1)
331 ; RV32I-NEXT: lhu s2, 4(a1)
332 ; RV32I-NEXT: lhu s3, 8(a1)
333 ; RV32I-NEXT: lhu s4, 12(a1)
334 ; RV32I-NEXT: mv s0, a0
335 ; RV32I-NEXT: li a1, 95
336 ; RV32I-NEXT: mv a0, s4
337 ; RV32I-NEXT: call __umodsi3
338 ; RV32I-NEXT: mv s5, a0
339 ; RV32I-NEXT: li a1, 95
340 ; RV32I-NEXT: mv a0, s3
341 ; RV32I-NEXT: call __umodsi3
342 ; RV32I-NEXT: mv s6, a0
343 ; RV32I-NEXT: li a1, 95
344 ; RV32I-NEXT: mv a0, s2
345 ; RV32I-NEXT: call __umodsi3
346 ; RV32I-NEXT: mv s7, a0
347 ; RV32I-NEXT: li a1, 95
348 ; RV32I-NEXT: mv a0, s1
349 ; RV32I-NEXT: call __umodsi3
350 ; RV32I-NEXT: mv s8, a0
351 ; RV32I-NEXT: li a1, 95
352 ; RV32I-NEXT: mv a0, s4
353 ; RV32I-NEXT: call __udivsi3
354 ; RV32I-NEXT: mv s4, a0
355 ; RV32I-NEXT: li a1, 95
356 ; RV32I-NEXT: mv a0, s3
357 ; RV32I-NEXT: call __udivsi3
358 ; RV32I-NEXT: mv s3, a0
359 ; RV32I-NEXT: li a1, 95
360 ; RV32I-NEXT: mv a0, s2
361 ; RV32I-NEXT: call __udivsi3
362 ; RV32I-NEXT: mv s2, a0
363 ; RV32I-NEXT: li a1, 95
364 ; RV32I-NEXT: mv a0, s1
365 ; RV32I-NEXT: call __udivsi3
366 ; RV32I-NEXT: add a0, s8, a0
367 ; RV32I-NEXT: add s2, s7, s2
368 ; RV32I-NEXT: add s3, s6, s3
369 ; RV32I-NEXT: add s4, s5, s4
370 ; RV32I-NEXT: sh s4, 6(s0)
371 ; RV32I-NEXT: sh s3, 4(s0)
372 ; RV32I-NEXT: sh s2, 2(s0)
373 ; RV32I-NEXT: sh a0, 0(s0)
374 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
375 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
376 ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
377 ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
378 ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
379 ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
380 ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
381 ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
382 ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
383 ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
384 ; RV32I-NEXT: addi sp, sp, 48
385 ; RV32I-NEXT: ret
386 ;
387 ; RV32IM-LABEL: combine_urem_udiv:
388 ; RV32IM: # %bb.0:
389 ; RV32IM-NEXT: lhu a2, 0(a1)
390 ; RV32IM-NEXT: lhu a3, 4(a1)
391 ; RV32IM-NEXT: lhu a4, 12(a1)
392 ; RV32IM-NEXT: lhu a1, 8(a1)
393 ; RV32IM-NEXT: lui a5, 11038
394 ; RV32IM-NEXT: addi a5, a5, -1465
395 ; RV32IM-NEXT: mulhu a6, a4, a5
396 ; RV32IM-NEXT: li a7, 95
397 ; RV32IM-NEXT: mul t0, a6, a7
398 ; RV32IM-NEXT: mulhu t1, a1, a5
399 ; RV32IM-NEXT: mul t2, t1, a7
400 ; RV32IM-NEXT: mulhu t3, a3, a5
401 ; RV32IM-NEXT: mul t4, t3, a7
402 ; RV32IM-NEXT: mulhu a5, a2, a5
403 ; RV32IM-NEXT: mul a7, a5, a7
404 ; RV32IM-NEXT: add a2, a2, a5
405 ; RV32IM-NEXT: sub a2, a2, a7
406 ; RV32IM-NEXT: add a3, a3, t3
407 ; RV32IM-NEXT: sub a3, a3, t4
408 ; RV32IM-NEXT: add a1, a1, t1
409 ; RV32IM-NEXT: sub a1, a1, t2
410 ; RV32IM-NEXT: add a4, a4, a6
411 ; RV32IM-NEXT: sub a4, a4, t0
412 ; RV32IM-NEXT: sh a4, 6(a0)
413 ; RV32IM-NEXT: sh a1, 4(a0)
414 ; RV32IM-NEXT: sh a3, 2(a0)
415 ; RV32IM-NEXT: sh a2, 0(a0)
416 ; RV32IM-NEXT: ret
417 ;
418 ; RV64I-LABEL: combine_urem_udiv:
419 ; RV64I: # %bb.0:
420 ; RV64I-NEXT: addi sp, sp, -80
421 ; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
422 ; RV64I-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
423 ; RV64I-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
424 ; RV64I-NEXT: sd s2, 48(sp) # 8-byte Folded Spill
425 ; RV64I-NEXT: sd s3, 40(sp) # 8-byte Folded Spill
426 ; RV64I-NEXT: sd s4, 32(sp) # 8-byte Folded Spill
427 ; RV64I-NEXT: sd s5, 24(sp) # 8-byte Folded Spill
428 ; RV64I-NEXT: sd s6, 16(sp) # 8-byte Folded Spill
429 ; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
430 ; RV64I-NEXT: sd s8, 0(sp) # 8-byte Folded Spill
431 ; RV64I-NEXT: lhu s1, 0(a1)
432 ; RV64I-NEXT: lhu s2, 8(a1)
433 ; RV64I-NEXT: lhu s3, 16(a1)
434 ; RV64I-NEXT: lhu s4, 24(a1)
435 ; RV64I-NEXT: mv s0, a0
436 ; RV64I-NEXT: li a1, 95
437 ; RV64I-NEXT: mv a0, s4
438 ; RV64I-NEXT: call __umoddi3
439 ; RV64I-NEXT: mv s5, a0
440 ; RV64I-NEXT: li a1, 95
441 ; RV64I-NEXT: mv a0, s3
442 ; RV64I-NEXT: call __umoddi3
443 ; RV64I-NEXT: mv s6, a0
444 ; RV64I-NEXT: li a1, 95
445 ; RV64I-NEXT: mv a0, s2
446 ; RV64I-NEXT: call __umoddi3
447 ; RV64I-NEXT: mv s7, a0
448 ; RV64I-NEXT: li a1, 95
449 ; RV64I-NEXT: mv a0, s1
450 ; RV64I-NEXT: call __umoddi3
451 ; RV64I-NEXT: mv s8, a0
452 ; RV64I-NEXT: li a1, 95
453 ; RV64I-NEXT: mv a0, s4
454 ; RV64I-NEXT: call __udivdi3
455 ; RV64I-NEXT: mv s4, a0
456 ; RV64I-NEXT: li a1, 95
457 ; RV64I-NEXT: mv a0, s3
458 ; RV64I-NEXT: call __udivdi3
459 ; RV64I-NEXT: mv s3, a0
460 ; RV64I-NEXT: li a1, 95
461 ; RV64I-NEXT: mv a0, s2
462 ; RV64I-NEXT: call __udivdi3
463 ; RV64I-NEXT: mv s2, a0
464 ; RV64I-NEXT: li a1, 95
465 ; RV64I-NEXT: mv a0, s1
466 ; RV64I-NEXT: call __udivdi3
467 ; RV64I-NEXT: add a0, s8, a0
468 ; RV64I-NEXT: add s2, s7, s2
469 ; RV64I-NEXT: add s3, s6, s3
470 ; RV64I-NEXT: add s4, s5, s4
471 ; RV64I-NEXT: sh s4, 6(s0)
472 ; RV64I-NEXT: sh s3, 4(s0)
473 ; RV64I-NEXT: sh s2, 2(s0)
474 ; RV64I-NEXT: sh a0, 0(s0)
475 ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
476 ; RV64I-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
477 ; RV64I-NEXT: ld s1, 56(sp) # 8-byte Folded Reload
478 ; RV64I-NEXT: ld s2, 48(sp) # 8-byte Folded Reload
479 ; RV64I-NEXT: ld s3, 40(sp) # 8-byte Folded Reload
480 ; RV64I-NEXT: ld s4, 32(sp) # 8-byte Folded Reload
481 ; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload
482 ; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload
483 ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
484 ; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload
485 ; RV64I-NEXT: addi sp, sp, 80
486 ; RV64I-NEXT: ret
487 ;
488 ; RV64IM-LABEL: combine_urem_udiv:
489 ; RV64IM: # %bb.0:
490 ; RV64IM-NEXT: lhu a2, 24(a1)
491 ; RV64IM-NEXT: lui a3, %hi(.LCPI2_0)
492 ; RV64IM-NEXT: ld a3, %lo(.LCPI2_0)(a3)
493 ; RV64IM-NEXT: lhu a4, 0(a1)
494 ; RV64IM-NEXT: lhu a5, 8(a1)
495 ; RV64IM-NEXT: lhu a1, 16(a1)
496 ; RV64IM-NEXT: mulhu a6, a2, a3
497 ; RV64IM-NEXT: li a7, 95
498 ; RV64IM-NEXT: mul t0, a6, a7
499 ; RV64IM-NEXT: mulhu t1, a1, a3
500 ; RV64IM-NEXT: mul t2, t1, a7
501 ; RV64IM-NEXT: mulhu t3, a5, a3
502 ; RV64IM-NEXT: mul t4, t3, a7
503 ; RV64IM-NEXT: mulhu a3, a4, a3
504 ; RV64IM-NEXT: mul a7, a3, a7
505 ; RV64IM-NEXT: add a3, a4, a3
506 ; RV64IM-NEXT: subw a3, a3, a7
507 ; RV64IM-NEXT: add a5, a5, t3
508 ; RV64IM-NEXT: subw a4, a5, t4
509 ; RV64IM-NEXT: add a1, a1, t1
510 ; RV64IM-NEXT: subw a1, a1, t2
511 ; RV64IM-NEXT: add a2, a2, a6
512 ; RV64IM-NEXT: subw a2, a2, t0
513 ; RV64IM-NEXT: sh a2, 6(a0)
514 ; RV64IM-NEXT: sh a1, 4(a0)
515 ; RV64IM-NEXT: sh a4, 2(a0)
516 ; RV64IM-NEXT: sh a3, 0(a0)
517 ; RV64IM-NEXT: ret
518 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
519 %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
520 %3 = add <4 x i16> %1, %2
521 ret <4 x i16> %3
522 }
524 ; Don't fold for divisors that are a power of two.
525 define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
526 ; RV32I-LABEL: dont_fold_urem_power_of_two:
527 ; RV32I: # %bb.0:
528 ; RV32I-NEXT: addi sp, sp, -32
529 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
530 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
531 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
532 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
533 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
534 ; RV32I-NEXT: lhu s1, 8(a1)
535 ; RV32I-NEXT: lhu s2, 4(a1)
536 ; RV32I-NEXT: lhu s3, 0(a1)
537 ; RV32I-NEXT: lhu a2, 12(a1)
538 ; RV32I-NEXT: mv s0, a0
539 ; RV32I-NEXT: li a1, 95
540 ; RV32I-NEXT: mv a0, a2
541 ; RV32I-NEXT: call __umodsi3
542 ; RV32I-NEXT: andi a1, s3, 63
543 ; RV32I-NEXT: andi a2, s2, 31
544 ; RV32I-NEXT: andi s1, s1, 7
545 ; RV32I-NEXT: sh a0, 6(s0)
546 ; RV32I-NEXT: sh s1, 4(s0)
547 ; RV32I-NEXT: sh a2, 2(s0)
548 ; RV32I-NEXT: sh a1, 0(s0)
549 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
550 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
551 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
552 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
553 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
554 ; RV32I-NEXT: addi sp, sp, 32
555 ; RV32I-NEXT: ret
556 ;
557 ; RV32IM-LABEL: dont_fold_urem_power_of_two:
558 ; RV32IM: # %bb.0:
559 ; RV32IM-NEXT: lhu a2, 8(a1)
560 ; RV32IM-NEXT: lhu a3, 4(a1)
561 ; RV32IM-NEXT: lhu a4, 12(a1)
562 ; RV32IM-NEXT: lhu a1, 0(a1)
563 ; RV32IM-NEXT: lui a5, 11038
564 ; RV32IM-NEXT: addi a5, a5, -1465
565 ; RV32IM-NEXT: mulhu a5, a4, a5
566 ; RV32IM-NEXT: li a6, 95
567 ; RV32IM-NEXT: mul a5, a5, a6
568 ; RV32IM-NEXT: sub a4, a4, a5
569 ; RV32IM-NEXT: andi a1, a1, 63
570 ; RV32IM-NEXT: andi a3, a3, 31
571 ; RV32IM-NEXT: andi a2, a2, 7
572 ; RV32IM-NEXT: sh a2, 4(a0)
573 ; RV32IM-NEXT: sh a3, 2(a0)
574 ; RV32IM-NEXT: sh a1, 0(a0)
575 ; RV32IM-NEXT: sh a4, 6(a0)
576 ; RV32IM-NEXT: ret
577 ;
578 ; RV64I-LABEL: dont_fold_urem_power_of_two:
579 ; RV64I: # %bb.0:
580 ; RV64I-NEXT: addi sp, sp, -48
581 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
582 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
583 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
584 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
585 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
586 ; RV64I-NEXT: lhu s1, 16(a1)
587 ; RV64I-NEXT: lhu s2, 8(a1)
588 ; RV64I-NEXT: lhu s3, 0(a1)
589 ; RV64I-NEXT: lhu a2, 24(a1)
590 ; RV64I-NEXT: mv s0, a0
591 ; RV64I-NEXT: li a1, 95
592 ; RV64I-NEXT: mv a0, a2
593 ; RV64I-NEXT: call __umoddi3
594 ; RV64I-NEXT: andi a1, s3, 63
595 ; RV64I-NEXT: andi a2, s2, 31
596 ; RV64I-NEXT: andi s1, s1, 7
597 ; RV64I-NEXT: sh a0, 6(s0)
598 ; RV64I-NEXT: sh s1, 4(s0)
599 ; RV64I-NEXT: sh a2, 2(s0)
600 ; RV64I-NEXT: sh a1, 0(s0)
601 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
602 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
603 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
604 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
605 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
606 ; RV64I-NEXT: addi sp, sp, 48
607 ; RV64I-NEXT: ret
608 ;
609 ; RV64IM-LABEL: dont_fold_urem_power_of_two:
610 ; RV64IM: # %bb.0:
611 ; RV64IM-NEXT: lhu a2, 24(a1)
612 ; RV64IM-NEXT: lui a3, %hi(.LCPI3_0)
613 ; RV64IM-NEXT: ld a3, %lo(.LCPI3_0)(a3)
614 ; RV64IM-NEXT: lhu a4, 16(a1)
615 ; RV64IM-NEXT: lhu a5, 8(a1)
616 ; RV64IM-NEXT: lhu a1, 0(a1)
617 ; RV64IM-NEXT: mulhu a3, a2, a3
618 ; RV64IM-NEXT: li a6, 95
619 ; RV64IM-NEXT: mul a3, a3, a6
620 ; RV64IM-NEXT: subw a2, a2, a3
621 ; RV64IM-NEXT: andi a1, a1, 63
622 ; RV64IM-NEXT: andi a5, a5, 31
623 ; RV64IM-NEXT: andi a4, a4, 7
624 ; RV64IM-NEXT: sh a4, 4(a0)
625 ; RV64IM-NEXT: sh a5, 2(a0)
626 ; RV64IM-NEXT: sh a1, 0(a0)
627 ; RV64IM-NEXT: sh a2, 6(a0)
628 ; RV64IM-NEXT: ret
629 %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
630 ret <4 x i16> %1
631 }
633 ; Don't fold if the divisor is one.
634 define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
635 ; RV32I-LABEL: dont_fold_urem_one:
636 ; RV32I: # %bb.0:
637 ; RV32I-NEXT: addi sp, sp, -32
638 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
639 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
640 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
641 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
642 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
643 ; RV32I-NEXT: lhu s0, 12(a1)
644 ; RV32I-NEXT: lhu s1, 8(a1)
645 ; RV32I-NEXT: lhu a2, 4(a1)
646 ; RV32I-NEXT: mv s2, a0
647 ; RV32I-NEXT: li a1, 654
648 ; RV32I-NEXT: mv a0, a2
649 ; RV32I-NEXT: call __umodsi3
650 ; RV32I-NEXT: mv s3, a0
651 ; RV32I-NEXT: li a1, 23
652 ; RV32I-NEXT: mv a0, s1
653 ; RV32I-NEXT: call __umodsi3
654 ; RV32I-NEXT: mv s1, a0
655 ; RV32I-NEXT: lui a0, 1
656 ; RV32I-NEXT: addi a1, a0, 1327
657 ; RV32I-NEXT: mv a0, s0
658 ; RV32I-NEXT: call __umodsi3
659 ; RV32I-NEXT: sh a0, 6(s2)
660 ; RV32I-NEXT: sh s1, 4(s2)
661 ; RV32I-NEXT: sh s3, 2(s2)
662 ; RV32I-NEXT: sh zero, 0(s2)
663 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
664 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
665 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
666 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
667 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
668 ; RV32I-NEXT: addi sp, sp, 32
669 ; RV32I-NEXT: ret
670 ;
671 ; RV32IM-LABEL: dont_fold_urem_one:
672 ; RV32IM: # %bb.0:
673 ; RV32IM-NEXT: lhu a2, 12(a1)
674 ; RV32IM-NEXT: lhu a3, 4(a1)
675 ; RV32IM-NEXT: lhu a1, 8(a1)
676 ; RV32IM-NEXT: lui a4, 1603
677 ; RV32IM-NEXT: addi a4, a4, 1341
678 ; RV32IM-NEXT: mulhu a4, a3, a4
679 ; RV32IM-NEXT: li a5, 654
680 ; RV32IM-NEXT: mul a4, a4, a5
681 ; RV32IM-NEXT: sub a3, a3, a4
682 ; RV32IM-NEXT: lui a4, 45590
683 ; RV32IM-NEXT: addi a4, a4, 1069
684 ; RV32IM-NEXT: mulhu a4, a1, a4
685 ; RV32IM-NEXT: li a5, 23
686 ; RV32IM-NEXT: mul a4, a4, a5
687 ; RV32IM-NEXT: sub a1, a1, a4
688 ; RV32IM-NEXT: lui a4, 193
689 ; RV32IM-NEXT: addi a4, a4, 1464
690 ; RV32IM-NEXT: mulhu a4, a2, a4
691 ; RV32IM-NEXT: lui a5, 1
692 ; RV32IM-NEXT: addi a5, a5, 1327
693 ; RV32IM-NEXT: mul a4, a4, a5
694 ; RV32IM-NEXT: sub a2, a2, a4
695 ; RV32IM-NEXT: sh zero, 0(a0)
696 ; RV32IM-NEXT: sh a2, 6(a0)
697 ; RV32IM-NEXT: sh a1, 4(a0)
698 ; RV32IM-NEXT: sh a3, 2(a0)
699 ; RV32IM-NEXT: ret
700 ;
701 ; RV64I-LABEL: dont_fold_urem_one:
702 ; RV64I: # %bb.0:
703 ; RV64I-NEXT: addi sp, sp, -48
704 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
705 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
706 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
707 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
708 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
709 ; RV64I-NEXT: lhu s0, 24(a1)
710 ; RV64I-NEXT: lhu s1, 16(a1)
711 ; RV64I-NEXT: lhu a2, 8(a1)
712 ; RV64I-NEXT: mv s2, a0
713 ; RV64I-NEXT: li a1, 654
714 ; RV64I-NEXT: mv a0, a2
715 ; RV64I-NEXT: call __umoddi3
716 ; RV64I-NEXT: mv s3, a0
717 ; RV64I-NEXT: li a1, 23
718 ; RV64I-NEXT: mv a0, s1
719 ; RV64I-NEXT: call __umoddi3
720 ; RV64I-NEXT: mv s1, a0
721 ; RV64I-NEXT: lui a0, 1
722 ; RV64I-NEXT: addiw a1, a0, 1327
723 ; RV64I-NEXT: mv a0, s0
724 ; RV64I-NEXT: call __umoddi3
725 ; RV64I-NEXT: sh a0, 6(s2)
726 ; RV64I-NEXT: sh s1, 4(s2)
727 ; RV64I-NEXT: sh s3, 2(s2)
728 ; RV64I-NEXT: sh zero, 0(s2)
729 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
730 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
731 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
732 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
733 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
734 ; RV64I-NEXT: addi sp, sp, 48
735 ; RV64I-NEXT: ret
736 ;
737 ; RV64IM-LABEL: dont_fold_urem_one:
738 ; RV64IM: # %bb.0:
739 ; RV64IM-NEXT: lhu a2, 8(a1)
740 ; RV64IM-NEXT: lui a3, %hi(.LCPI4_0)
741 ; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3)
742 ; RV64IM-NEXT: lhu a4, 24(a1)
743 ; RV64IM-NEXT: lhu a1, 16(a1)
744 ; RV64IM-NEXT: mulhu a3, a2, a3
745 ; RV64IM-NEXT: lui a5, %hi(.LCPI4_1)
746 ; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5)
747 ; RV64IM-NEXT: li a6, 654
748 ; RV64IM-NEXT: mul a3, a3, a6
749 ; RV64IM-NEXT: subw a2, a2, a3
750 ; RV64IM-NEXT: mulhu a3, a1, a5
751 ; RV64IM-NEXT: lui a5, %hi(.LCPI4_2)
752 ; RV64IM-NEXT: ld a5, %lo(.LCPI4_2)(a5)
753 ; RV64IM-NEXT: li a6, 23
754 ; RV64IM-NEXT: mul a3, a3, a6
755 ; RV64IM-NEXT: subw a1, a1, a3
756 ; RV64IM-NEXT: mulhu a3, a4, a5
757 ; RV64IM-NEXT: lui a5, 1
758 ; RV64IM-NEXT: addi a5, a5, 1327
759 ; RV64IM-NEXT: mul a3, a3, a5
760 ; RV64IM-NEXT: subw a4, a4, a3
761 ; RV64IM-NEXT: sh zero, 0(a0)
762 ; RV64IM-NEXT: sh a4, 6(a0)
763 ; RV64IM-NEXT: sh a1, 4(a0)
764 ; RV64IM-NEXT: sh a2, 2(a0)
765 ; RV64IM-NEXT: ret
766 %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
767 ret <4 x i16> %1
768 }
770 ; Don't fold if the divisor is 2^16.
771 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
772 ; CHECK-LABEL: dont_fold_urem_i16_smax:
773 ; CHECK: # %bb.0:
774 ; CHECK-NEXT: ret
775 %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
776 ret <4 x i16> %1
777 }
779 ; Don't fold i64 urem.
780 define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
781 ; RV32I-LABEL: dont_fold_urem_i64:
782 ; RV32I: # %bb.0:
783 ; RV32I-NEXT: addi sp, sp, -48
784 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
785 ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
786 ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
787 ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
788 ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
789 ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
790 ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
791 ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
792 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
793 ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
794 ; RV32I-NEXT: lw s0, 24(a1)
795 ; RV32I-NEXT: lw s1, 28(a1)
796 ; RV32I-NEXT: lw s2, 16(a1)
797 ; RV32I-NEXT: lw s3, 20(a1)
798 ; RV32I-NEXT: lw s4, 8(a1)
799 ; RV32I-NEXT: lw s5, 12(a1)
800 ; RV32I-NEXT: lw a3, 0(a1)
801 ; RV32I-NEXT: lw a1, 4(a1)
802 ; RV32I-NEXT: mv s6, a0
803 ; RV32I-NEXT: li a2, 1
804 ; RV32I-NEXT: mv a0, a3
805 ; RV32I-NEXT: li a3, 0
806 ; RV32I-NEXT: call __umoddi3
807 ; RV32I-NEXT: mv s7, a0
808 ; RV32I-NEXT: mv s8, a1
809 ; RV32I-NEXT: li a2, 654
810 ; RV32I-NEXT: mv a0, s4
811 ; RV32I-NEXT: mv a1, s5
812 ; RV32I-NEXT: li a3, 0
813 ; RV32I-NEXT: call __umoddi3
814 ; RV32I-NEXT: mv s4, a0
815 ; RV32I-NEXT: mv s5, a1
816 ; RV32I-NEXT: li a2, 23
817 ; RV32I-NEXT: mv a0, s2
818 ; RV32I-NEXT: mv a1, s3
819 ; RV32I-NEXT: li a3, 0
820 ; RV32I-NEXT: call __umoddi3
821 ; RV32I-NEXT: mv s2, a0
822 ; RV32I-NEXT: mv s3, a1
823 ; RV32I-NEXT: lui a0, 1
824 ; RV32I-NEXT: addi a2, a0, 1327
825 ; RV32I-NEXT: mv a0, s0
826 ; RV32I-NEXT: mv a1, s1
827 ; RV32I-NEXT: li a3, 0
828 ; RV32I-NEXT: call __umoddi3
829 ; RV32I-NEXT: sw a1, 28(s6)
830 ; RV32I-NEXT: sw a0, 24(s6)
831 ; RV32I-NEXT: sw s3, 20(s6)
832 ; RV32I-NEXT: sw s2, 16(s6)
833 ; RV32I-NEXT: sw s5, 12(s6)
834 ; RV32I-NEXT: sw s4, 8(s6)
835 ; RV32I-NEXT: sw s8, 4(s6)
836 ; RV32I-NEXT: sw s7, 0(s6)
837 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
838 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
839 ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
840 ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
841 ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
842 ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
843 ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
844 ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
845 ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
846 ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
847 ; RV32I-NEXT: addi sp, sp, 48
848 ; RV32I-NEXT: ret
849 ;
850 ; RV32IM-LABEL: dont_fold_urem_i64:
851 ; RV32IM: # %bb.0:
852 ; RV32IM-NEXT: addi sp, sp, -48
853 ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
854 ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
855 ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
856 ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
857 ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
858 ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
859 ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
860 ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
861 ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
862 ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
863 ; RV32IM-NEXT: lw s0, 24(a1)
864 ; RV32IM-NEXT: lw s1, 28(a1)
865 ; RV32IM-NEXT: lw s2, 16(a1)
866 ; RV32IM-NEXT: lw s3, 20(a1)
867 ; RV32IM-NEXT: lw s4, 8(a1)
868 ; RV32IM-NEXT: lw s5, 12(a1)
869 ; RV32IM-NEXT: lw a3, 0(a1)
870 ; RV32IM-NEXT: lw a1, 4(a1)
871 ; RV32IM-NEXT: mv s6, a0
872 ; RV32IM-NEXT: li a2, 1
873 ; RV32IM-NEXT: mv a0, a3
874 ; RV32IM-NEXT: li a3, 0
875 ; RV32IM-NEXT: call __umoddi3
876 ; RV32IM-NEXT: mv s7, a0
877 ; RV32IM-NEXT: mv s8, a1
878 ; RV32IM-NEXT: li a2, 654
879 ; RV32IM-NEXT: mv a0, s4
880 ; RV32IM-NEXT: mv a1, s5
881 ; RV32IM-NEXT: li a3, 0
882 ; RV32IM-NEXT: call __umoddi3
883 ; RV32IM-NEXT: mv s4, a0
884 ; RV32IM-NEXT: mv s5, a1
885 ; RV32IM-NEXT: li a2, 23
886 ; RV32IM-NEXT: mv a0, s2
887 ; RV32IM-NEXT: mv a1, s3
888 ; RV32IM-NEXT: li a3, 0
889 ; RV32IM-NEXT: call __umoddi3
890 ; RV32IM-NEXT: mv s2, a0
891 ; RV32IM-NEXT: mv s3, a1
892 ; RV32IM-NEXT: lui a0, 1
893 ; RV32IM-NEXT: addi a2, a0, 1327
894 ; RV32IM-NEXT: mv a0, s0
895 ; RV32IM-NEXT: mv a1, s1
896 ; RV32IM-NEXT: li a3, 0
897 ; RV32IM-NEXT: call __umoddi3
898 ; RV32IM-NEXT: sw a1, 28(s6)
899 ; RV32IM-NEXT: sw a0, 24(s6)
900 ; RV32IM-NEXT: sw s3, 20(s6)
901 ; RV32IM-NEXT: sw s2, 16(s6)
902 ; RV32IM-NEXT: sw s5, 12(s6)
903 ; RV32IM-NEXT: sw s4, 8(s6)
904 ; RV32IM-NEXT: sw s8, 4(s6)
905 ; RV32IM-NEXT: sw s7, 0(s6)
906 ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
907 ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
908 ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
909 ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
910 ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
911 ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
912 ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
913 ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
914 ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
915 ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
916 ; RV32IM-NEXT: addi sp, sp, 48
917 ; RV32IM-NEXT: ret
918 ;
919 ; RV64I-LABEL: dont_fold_urem_i64:
920 ; RV64I: # %bb.0:
921 ; RV64I-NEXT: addi sp, sp, -48
922 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
923 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
924 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
925 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
926 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
927 ; RV64I-NEXT: ld s0, 24(a1)
928 ; RV64I-NEXT: ld s1, 16(a1)
929 ; RV64I-NEXT: ld a2, 8(a1)
930 ; RV64I-NEXT: mv s2, a0
931 ; RV64I-NEXT: li a1, 654
932 ; RV64I-NEXT: mv a0, a2
933 ; RV64I-NEXT: call __umoddi3
934 ; RV64I-NEXT: mv s3, a0
935 ; RV64I-NEXT: li a1, 23
936 ; RV64I-NEXT: mv a0, s1
937 ; RV64I-NEXT: call __umoddi3
938 ; RV64I-NEXT: mv s1, a0
939 ; RV64I-NEXT: lui a0, 1
940 ; RV64I-NEXT: addiw a1, a0, 1327
941 ; RV64I-NEXT: mv a0, s0
942 ; RV64I-NEXT: call __umoddi3
943 ; RV64I-NEXT: sd a0, 24(s2)
944 ; RV64I-NEXT: sd s1, 16(s2)
945 ; RV64I-NEXT: sd s3, 8(s2)
946 ; RV64I-NEXT: sd zero, 0(s2)
947 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
948 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
949 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
950 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
951 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
952 ; RV64I-NEXT: addi sp, sp, 48
953 ; RV64I-NEXT: ret
954 ;
955 ; RV64IM-LABEL: dont_fold_urem_i64:
956 ; RV64IM: # %bb.0:
957 ; RV64IM-NEXT: ld a2, 16(a1)
958 ; RV64IM-NEXT: lui a3, %hi(.LCPI6_0)
959 ; RV64IM-NEXT: ld a3, %lo(.LCPI6_0)(a3)
960 ; RV64IM-NEXT: ld a4, 24(a1)
961 ; RV64IM-NEXT: ld a1, 8(a1)
962 ; RV64IM-NEXT: mulhu a3, a2, a3
963 ; RV64IM-NEXT: sub a5, a2, a3
964 ; RV64IM-NEXT: srli a5, a5, 1
965 ; RV64IM-NEXT: add a3, a5, a3
966 ; RV64IM-NEXT: srli a3, a3, 4
967 ; RV64IM-NEXT: li a5, 23
968 ; RV64IM-NEXT: lui a6, %hi(.LCPI6_1)
969 ; RV64IM-NEXT: ld a6, %lo(.LCPI6_1)(a6)
970 ; RV64IM-NEXT: mul a3, a3, a5
971 ; RV64IM-NEXT: sub a2, a2, a3
972 ; RV64IM-NEXT: srli a3, a1, 1
973 ; RV64IM-NEXT: mulhu a3, a3, a6
974 ; RV64IM-NEXT: srli a3, a3, 7
975 ; RV64IM-NEXT: lui a5, %hi(.LCPI6_2)
976 ; RV64IM-NEXT: ld a5, %lo(.LCPI6_2)(a5)
977 ; RV64IM-NEXT: li a6, 654
978 ; RV64IM-NEXT: mul a3, a3, a6
979 ; RV64IM-NEXT: sub a1, a1, a3
980 ; RV64IM-NEXT: mulhu a3, a4, a5
981 ; RV64IM-NEXT: srli a3, a3, 12
982 ; RV64IM-NEXT: lui a5, 1
983 ; RV64IM-NEXT: addiw a5, a5, 1327
984 ; RV64IM-NEXT: mul a3, a3, a5
985 ; RV64IM-NEXT: sub a4, a4, a3
986 ; RV64IM-NEXT: sd zero, 0(a0)
987 ; RV64IM-NEXT: sd a4, 24(a0)
988 ; RV64IM-NEXT: sd a1, 8(a0)
989 ; RV64IM-NEXT: sd a2, 16(a0)
990 ; RV64IM-NEXT: ret
991 %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
992 ret <4 x i64> %1
993 }