1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s
4 target triple = "aarch64-unknown-linux-gnu"
6 define void @trip1025_i64(ptr noalias nocapture noundef %dst, ptr noalias nocapture noundef readonly %src) #0 {
7 ; CHECK-LABEL: @trip1025_i64(
9 ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
11 ; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
12 ; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2
13 ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
14 ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 2
15 ; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[TMP3]], 1
16 ; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 1025, [[TMP4]]
17 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]]
18 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
19 ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
20 ; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2
21 ; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 1025)
22 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
24 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
25 ; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ]
26 ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 0
27 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[SRC:%.*]], i64 [[TMP7]]
28 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP8]], i32 0
29 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP9]], i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)
30 ; CHECK-NEXT: [[TMP10:%.*]] = shl nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
31 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST:%.*]], i64 [[TMP7]]
32 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP11]], i32 0
33 ; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0(ptr [[TMP12]], i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)
34 ; CHECK-NEXT: [[TMP13:%.*]] = add nsw <vscale x 2 x i64> [[WIDE_MASKED_LOAD1]], [[TMP10]]
35 ; CHECK-NEXT: call void @llvm.masked.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP13]], ptr [[TMP12]], i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])
36 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]]
37 ; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[INDEX_NEXT]], i64 1025)
38 ; CHECK-NEXT: [[TMP14:%.*]] = xor <vscale x 2 x i1> [[ACTIVE_LANE_MASK_NEXT]], shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer)
39 ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <vscale x 2 x i1> [[TMP14]], i32 0
40 ; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
41 ; CHECK: middle.block:
42 ; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
44 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
45 ; CHECK-NEXT: br label [[FOR_BODY:%.*]]
47 ; CHECK-NEXT: [[I_06:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
48 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[I_06]]
49 ; CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
50 ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[TMP16]], 1
51 ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[I_06]]
52 ; CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8
53 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP17]], [[MUL]]
54 ; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX1]], align 8
55 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[I_06]], 1
56 ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], 1025
57 ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
59 ; CHECK-NEXT: ret void
64 for.body: ; preds = %entry, %for.body
65 %i.06 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
66 %arrayidx = getelementptr inbounds i64, ptr %src, i64 %i.06
67 %0 = load i64, ptr %arrayidx, align 8
68 %mul = shl nsw i64 %0, 1
69 %arrayidx1 = getelementptr inbounds i64, ptr %dst, i64 %i.06
70 %1 = load i64, ptr %arrayidx1, align 8
71 %add = add nsw i64 %1, %mul
72 store i64 %add, ptr %arrayidx1, align 8
73 %inc = add nuw nsw i64 %i.06, 1
74 %exitcond.not = icmp eq i64 %inc, 1025
75 br i1 %exitcond.not, label %for.end, label %for.body
77 for.end: ; preds = %for.body
81 attributes #0 = { vscale_range(1,16) "target-features"="+sve" optsize }