[AMDGPU] New gfx940 mfma instructions
[llvm-project.git] / llvm / lib / Target / AArch64 / AArch64PBQPRegAlloc.h
blob5ea91b4a1967b9cb321c60dee5c85e7196a1f353
1 //==- AArch64PBQPRegAlloc.h - AArch64 specific PBQP constraints --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
10 #define LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
12 #include "llvm/ADT/SetVector.h"
13 #include "llvm/CodeGen/PBQPRAConstraint.h"
15 namespace llvm {
17 class TargetRegisterInfo;
19 /// Add the accumulator chaining constraint to a PBQP graph
20 class A57ChainingConstraint : public PBQPRAConstraint {
21 public:
22 // Add A57 specific constraints to the PBQP graph.
23 void apply(PBQPRAGraph &G) override;
25 private:
26 SmallSetVector<unsigned, 32> Chains;
27 const TargetRegisterInfo *TRI;
29 // Add the accumulator chaining constraint, inside the chain, i.e. so that
30 // parity(Rd) == parity(Ra).
31 // \return true if a constraint was added
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
34 // Add constraints between existing chains
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
38 } // end namespace llvm
40 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H