flang/test/Lower/submodule.f90

   1 ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s
   2
   3 module mm
   4   integer :: vv = 20
   5   interface
   6     module function ff1(nn)
   7       integer ff1(nn+1)
   8     end function ff1
   9     module function ff2(nn)
  10       integer ff2(nn+2)
  11     end function ff2
  12     module function ff3(nn)
  13       integer ff3(nn+3)
  14     end function ff3
  15   end interface
  16 end module mm
  17
  18 submodule(mm) ss1
  19   integer :: ww = 20
  20   interface
  21     module function fff(nn)
  22       integer fff
  23     end function fff
  24   end interface
  25 contains
  26   ! CHECK-LABEL: func @_QMmmPff2
  27   ! CHECK:     %[[V_0:[0-9]+]] = fir.load %arg0 : !fir.ref<i32>
  28   ! CHECK:     %[[V_1:[0-9]+]] = arith.addi %[[V_0]], %c2{{.*}} : i32
  29   ! CHECK:     %[[V_2:[0-9]+]] = fir.convert %[[V_1]] : (i32) -> i64
  30   ! CHECK:     %[[V_3:[0-9]+]] = fir.convert %[[V_2]] : (i64) -> index
  31   ! CHECK:     %[[V_4:[0-9]+]] = arith.cmpi sgt, %[[V_3]], %c0{{.*}} : index
  32   ! CHECK:     %[[V_5:[0-9]+]] = arith.select %[[V_4]], %[[V_3]], %c0{{.*}} : index
  33   ! CHECK:     %[[V_6:[0-9]+]] = fir.alloca !fir.array<?xi32>, %[[V_5]] {bindc_name = "ff2", uniq_name = "_QMmmSss1Fff2Eff2"}
  34   ! CHECK:     %[[V_7:[0-9]+]] = fir.shape %[[V_5]] : (index) -> !fir.shape<1>
  35   ! CHECK:     %[[V_8:[0-9]+]] = fir.array_load %[[V_6]](%[[V_7]]) : (!fir.ref<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.array<?xi32>
  36   ! CHECK:     %[[V_9:[0-9]+]] = fir.call @_QMmmSss1Pfff(%arg0) {{.*}} : (!fir.ref<i32>) -> i32
  37   ! CHECK:     %[[V_10:[0-9]+]] = arith.subi %[[V_5]], %c1{{.*}} : index
  38   ! CHECK:     %[[V_11:[0-9]+]] = fir.do_loop %arg1 = %c0{{.*}} to %[[V_10]] step %c1{{.*}} unordered iter_args(%arg2 = %[[V_8]]) -> (!fir.array<?xi32>) {
  39   ! CHECK:       %[[V_13:[0-9]+]] = fir.array_update %arg2, %[[V_9]], %arg1 : (!fir.array<?xi32>, i32, index) -> !fir.array<?xi32>
  40   ! CHECK:       fir.result %[[V_13]] : !fir.array<?xi32>
  41   ! CHECK:     }
  42   ! CHECK:     fir.array_merge_store %[[V_8]], %[[V_11]] to %[[V_6]] : !fir.array<?xi32>, !fir.array<?xi32>, !fir.ref<!fir.array<?xi32>>
  43   ! CHECK:     %[[V_12:[0-9]+]] = fir.load %[[V_6]] : !fir.ref<!fir.array<?xi32>>
  44   ! CHECK:     return %[[V_12]] : !fir.array<?xi32>
  45   ! CHECK:   }
  46   module procedure ff2
  47     ff2 = fff(nn)
  48   end procedure ff2
  49 end submodule ss1
  50
  51 submodule(mm:ss1) ss2
  52 contains
  53   ! CHECK-LABEL: func @_QMmmPff1
  54   ! CHECK-DAG: %[[V_0:[0-9]+]] = fir.address_of(@_QMmmEvv) : !fir.ref<i32>
  55   ! CHECK-DAG: %[[V_1:[0-9]+]] = fir.load %arg0 : !fir.ref<i32>
  56   ! CHECK:     %[[V_2:[0-9]+]] = arith.addi %[[V_1]], %c1{{.*}} : i32
  57   ! CHECK:     %[[V_3:[0-9]+]] = fir.convert %[[V_2]] : (i32) -> i64
  58   ! CHECK:     %[[V_4:[0-9]+]] = fir.convert %[[V_3]] : (i64) -> index
  59   ! CHECK:     %[[V_5:[0-9]+]] = arith.cmpi sgt, %[[V_4]], %c0{{.*}} : index
  60   ! CHECK:     %[[V_6:[0-9]+]] = arith.select %[[V_5]], %[[V_4]], %c0{{.*}} : index
  61   ! CHECK:     %[[V_7:[0-9]+]] = fir.alloca !fir.array<?xi32>, %[[V_6]] {bindc_name = "ff1", uniq_name = "_QMmmSss1Sss2Fff1Eff1"}
  62   ! CHECK:     %[[V_8:[0-9]+]] = fir.shape %[[V_6]] : (index) -> !fir.shape<1>
  63   ! CHECK:     %[[V_9:[0-9]+]] = fir.array_load %[[V_7]](%[[V_8]]) : (!fir.ref<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.array<?xi32>
  64   ! CHECK:     %[[V_10:[0-9]+]] = fir.load %[[V_0]] : !fir.ref<i32>
  65   ! CHECK:     %[[V_11:[0-9]+]] = arith.addi %[[V_10]], %c2{{.*}} : i32
  66   ! CHECK:     %[[V_12:[0-9]+]] = arith.subi %[[V_6]], %c1{{.*}} : index
  67   ! CHECK:     %[[V_13:[0-9]+]] = fir.do_loop %arg1 = %c0{{.*}} to %[[V_12]] step %c1{{.*}} unordered iter_args(%arg2 = %[[V_9]]) -> (!fir.array<?xi32>) {
  68   ! CHECK:       %[[V_15:[0-9]+]] = fir.array_update %arg2, %[[V_11]], %arg1 : (!fir.array<?xi32>, i32, index) -> !fir.array<?xi32>
  69   ! CHECK:       fir.result %[[V_15]] : !fir.array<?xi32>
  70   ! CHECK:     }
  71   ! CHECK:     fir.array_merge_store %[[V_9]], %[[V_13]] to %[[V_7]] : !fir.array<?xi32>, !fir.array<?xi32>, !fir.ref<!fir.array<?xi32>>
  72   ! CHECK:     %[[V_14:[0-9]+]] = fir.load %[[V_7]] : !fir.ref<!fir.array<?xi32>>
  73   ! CHECK:     return %[[V_14]] : !fir.array<?xi32>
  74   ! CHECK:   }
  75   module function ff1(nn)
  76     integer ff1(nn+1)
  77     ff1 = vv + 2
  78   end function ff1
  79
  80   ! CHECK-LABEL: func @_QMmmSss1Pfff
  81   ! CHECK-DAG: %[[V_0:[0-9]+]] = fir.address_of(@_QMmmSss1Eww) : !fir.ref<i32>
  82   ! CHECK-DAG: %[[V_1:[0-9]+]] = fir.address_of(@_QMmmEvv) : !fir.ref<i32>
  83   ! CHECK-DAG: %[[V_2:[0-9]+]] = fir.alloca i32 {bindc_name = "fff", uniq_name = "_QMmmSss1Sss2FfffEfff"}
  84   ! CHECK-DAG: %[[V_3:[0-9]+]] = fir.load %[[V_1]] : !fir.ref<i32>
  85   ! CHECK-DAG: %[[V_4:[0-9]+]] = fir.load %[[V_0]] : !fir.ref<i32>
  86   ! CHECK:     %[[V_5:[0-9]+]] = arith.addi %[[V_3]], %[[V_4]] : i32
  87   ! CHECK:     %[[V_6:[0-9]+]] = arith.addi %[[V_5]], %c4{{.*}} : i32
  88   ! CHECK:     fir.store %[[V_6]] to %[[V_2]] : !fir.ref<i32>
  89   ! CHECK:     %[[V_7:[0-9]+]] = fir.load %[[V_2]] : !fir.ref<i32>
  90   ! CHECK:     return %[[V_7]] : i32
  91   ! CHECK:   }
  92   module procedure fff
  93     fff = vv + ww + 4
  94   end procedure fff
  95 end submodule ss2
  96
  97 submodule(mm) sss
  98 contains
  99   ! CHECK-LABEL: func @_QMmmPff3
 100   ! CHECK-DAG: %[[V_0:[0-9]+]] = fir.address_of(@_QMmmEvv) : !fir.ref<i32>
 101   ! CHECK-DAG: %[[V_1:[0-9]+]] = fir.load %arg0 : !fir.ref<i32>
 102   ! CHECK:     %[[V_2:[0-9]+]] = arith.addi %[[V_1]], %c3{{.*}} : i32
 103   ! CHECK:     %[[V_3:[0-9]+]] = fir.convert %[[V_2]] : (i32) -> i64
 104   ! CHECK:     %[[V_4:[0-9]+]] = fir.convert %[[V_3]] : (i64) -> index
 105   ! CHECK:     %[[V_5:[0-9]+]] = arith.cmpi sgt, %[[V_4]], %c0{{.*}} : index
 106   ! CHECK:     %[[V_6:[0-9]+]] = arith.select %[[V_5]], %[[V_4]], %c0{{.*}} : index
 107   ! CHECK:     %[[V_7:[0-9]+]] = fir.alloca !fir.array<?xi32>, %[[V_6]] {bindc_name = "ff3", uniq_name = "_QMmmSsssFff3Eff3"}
 108   ! CHECK:     %[[V_8:[0-9]+]] = fir.shape %[[V_6]] : (index) -> !fir.shape<1>
 109   ! CHECK:     %[[V_9:[0-9]+]] = fir.array_load %[[V_7]](%[[V_8]]) : (!fir.ref<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.array<?xi32>
 110   ! CHECK-DAG: %[[V_10:[0-9]+]] = fir.load %arg0 : !fir.ref<i32>
 111   ! CHECK-DAG: %[[V_11:[0-9]+]] = fir.load %[[V_0]] : !fir.ref<i32>
 112   ! CHECK:     %[[V_12:[0-9]+]] = arith.muli %[[V_10]], %[[V_11]] : i32
 113   ! CHECK:     %[[V_13:[0-9]+]] = arith.addi %[[V_12]], %c6{{.*}} : i32
 114   ! CHECK:     %[[V_14:[0-9]+]] = arith.subi %[[V_6]], %c1{{.*}} : index
 115   ! CHECK:     %[[V_15:[0-9]+]] = fir.do_loop %arg1 = %c0{{.*}} to %[[V_14]] step %c1{{.*}} unordered iter_args(%arg2 = %[[V_9]]) -> (!fir.array<?xi32>) {
 116   ! CHECK:       %[[V_17:[0-9]+]] = fir.array_update %arg2, %[[V_13]], %arg1 : (!fir.array<?xi32>, i32, index) -> !fir.array<?xi32>
 117   ! CHECK:       fir.result %[[V_17]] : !fir.array<?xi32>
 118   ! CHECK:     }
 119   ! CHECK:     fir.array_merge_store %[[V_9]], %[[V_15]] to %[[V_7]] : !fir.array<?xi32>, !fir.array<?xi32>, !fir.ref<!fir.array<?xi32>>
 120   ! CHECK:     %[[V_16:[0-9]+]] = fir.load %[[V_7]] : !fir.ref<!fir.array<?xi32>>
 121   ! CHECK:     return %[[V_16]] : !fir.array<?xi32>
 122   ! CHECK:   }
 123   module function ff3(nn)
 124     integer ff3(nn+3)
 125     ff3 = nn*vv + 6
 126   end function ff3
 127 end submodule sss
 128
 129 ! CHECK-LABEL: func @_QQmain
 130 program pp
 131   use mm
 132   ! CHECK:     fir.call @_QMmmPff1(%{{[0-9]+}}) {{.*}} : (!fir.ref<i32>) -> !fir.array<?xi32>
 133   print*, ff1(1) ! expect: 22 22
 134   ! CHECK:     fir.call @_QMmmPff2(%{{[0-9]+}}) {{.*}} : (!fir.ref<i32>) -> !fir.array<?xi32>
 135   print*, ff2(2) ! expect: 44 44 44 44
 136   ! CHECK:     fir.call @_QMmmPff3(%{{[0-9]+}}) {{.*}} : (!fir.ref<i32>) -> !fir.array<?xi32>
 137   print*, ff3(3) ! expect: 66 66 66 66 66 66
 138 end program pp