1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
5 define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
6 define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}
7 define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}
8 define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
9 define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}
10 define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}
14 name: load1_s8_to_zextLoad1_s32
17 tracksRegLiveness: true
22 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
23 ; MIPS32: liveins: $a0
24 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
25 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
26 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
27 ; MIPS32: RetRA implicit $v0
29 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
35 name: load2_s16_to_zextLoad2_s32
38 tracksRegLiveness: true
43 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
44 ; MIPS32: liveins: $a0
45 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
46 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
47 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
48 ; MIPS32: RetRA implicit $v0
50 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
56 name: load4_s32_to_zextLoad4_s64
59 tracksRegLiveness: true
64 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
65 ; MIPS32: liveins: $a0
66 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
67 ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
68 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
69 ; MIPS32: $v0 = COPY [[LOAD]](s32)
70 ; MIPS32: $v1 = COPY [[C]](s32)
71 ; MIPS32: RetRA implicit $v0, implicit $v1
73 %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
74 %6:_(s32) = G_CONSTANT i32 0
75 %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
76 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
79 RetRA implicit $v0, implicit $v1
83 name: load1_s8_to_sextLoad1_s32
86 tracksRegLiveness: true
91 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
92 ; MIPS32: liveins: $a0
93 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
94 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
95 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
96 ; MIPS32: RetRA implicit $v0
98 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
104 name: load2_s16_to_sextLoad2_s32
107 tracksRegLiveness: true
112 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
113 ; MIPS32: liveins: $a0
114 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
115 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
116 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
117 ; MIPS32: RetRA implicit $v0
119 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
125 name: load4_s32_to_sextLoad4_s64
128 tracksRegLiveness: true
133 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
134 ; MIPS32: liveins: $a0
135 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
136 ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
137 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
138 ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
139 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
140 ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
141 ; MIPS32: $v0 = COPY [[LOAD]](s32)
142 ; MIPS32: $v1 = COPY [[ASHR]](s32)
143 ; MIPS32: RetRA implicit $v0, implicit $v1
145 %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
146 %9:_(s32) = G_CONSTANT i32 31
147 %10:_(s32) = G_CONSTANT i32 0
148 %8:_(s32) = COPY %9(s32)
149 %7:_(s32) = G_ASHR %5, %8(s32)
150 %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
151 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
154 RetRA implicit $v0, implicit $v1