1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
3 # RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
9 tracksRegLiveness: true
12 liveins: $x10, $f10_f, $f11_f
14 ; CHECK-LABEL: name: fp_select_s32
15 ; CHECK: liveins: $x10, $f10_f, $f11_f
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
19 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
20 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
21 ; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
22 ; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
23 ; CHECK-NEXT: PseudoRET implicit $f10_f
24 %0:gprb(s32) = COPY $x10
25 %1:fprb(s32) = COPY $f10_f
26 %2:fprb(s32) = COPY $f11_f
27 %3:gprb(s32) = G_CONSTANT i32 1
28 %4:gprb(s32) = G_AND %0, %3
29 %5:fprb(s32) = G_SELECT %4(s32), %1, %2
31 PseudoRET implicit $f10_f
38 tracksRegLiveness: true
41 liveins: $x10, $f10_d, $f11_d
43 ; CHECK-LABEL: name: fp_select_s64
44 ; CHECK: liveins: $x10, $f10_d, $f11_d
46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
47 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
48 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d
49 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
50 ; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
51 ; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]]
52 ; CHECK-NEXT: PseudoRET implicit $f10_d
53 %0:gprb(s32) = COPY $x10
54 %1:fprb(s64) = COPY $f10_d
55 %2:fprb(s64) = COPY $f11_d
56 %3:gprb(s32) = G_CONSTANT i32 1
57 %4:gprb(s32) = G_AND %0, %3
58 %5:fprb(s64) = G_SELECT %4(s32), %1, %2
60 PseudoRET implicit $f10_d