1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2 # RUN: llc -mtriple=riscv64 -run-pass=instruction-select \
3 # RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
9 tracksRegLiveness: true
14 ; CHECK-LABEL: name: shl
15 ; CHECK: liveins: $x10, $x11
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
20 ; CHECK-NEXT: $x10 = COPY [[SLL]]
21 ; CHECK-NEXT: PseudoRET implicit $x10
22 %0:gprb(s64) = COPY $x10
23 %1:gprb(s64) = COPY $x11
24 %3:gprb(s64) = G_SHL %0, %1
26 PseudoRET implicit $x10
33 tracksRegLiveness: true
38 ; CHECK-LABEL: name: shl_zext
39 ; CHECK: liveins: $x10
41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
42 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
43 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ADDI]]
44 ; CHECK-NEXT: $x10 = COPY [[SLL]]
45 ; CHECK-NEXT: PseudoRET implicit $x10
46 %0:gprb(s64) = COPY $x10
47 %1:gprb(s32) = G_CONSTANT i32 1
48 %2:gprb(s64) = G_ZEXT %1
49 %3:gprb(s64) = G_SHL %0, %2(s64)
51 PseudoRET implicit $x10
58 tracksRegLiveness: true
63 ; CHECK-LABEL: name: shl_and
64 ; CHECK: liveins: $x10, $x11
66 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
67 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
68 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
69 ; CHECK-NEXT: $x10 = COPY [[SLL]]
70 ; CHECK-NEXT: PseudoRET implicit $x10
71 %0:gprb(s64) = COPY $x10
72 %1:gprb(s64) = COPY $x11
73 %2:gprb(s64) = G_CONSTANT i64 63
74 %3:gprb(s64) = G_AND %1, %2
75 %4:gprb(s64) = G_SHL %0, %3(s64)
77 PseudoRET implicit $x10
81 name: shl_and_with_simplified_mask
84 tracksRegLiveness: true
89 ; CHECK-LABEL: name: shl_and_with_simplified_mask
90 ; CHECK: liveins: $x10, $x11
92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
93 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
94 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 62
95 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]]
96 ; CHECK-NEXT: $x10 = COPY [[SLL]]
97 ; CHECK-NEXT: PseudoRET implicit $x10
98 %0:gprb(s64) = COPY $x10
99 %1:gprb(s64) = COPY $x11
100 %2:gprb(s64) = G_CONSTANT i64 62
101 %3:gprb(s64) = G_AND %1, %2
102 %4:gprb(s64) = G_CONSTANT i64 62
103 %5:gprb(s64) = G_AND %3, %4
104 %6:gprb(s64) = G_SHL %0, %5(s64)
106 PseudoRET implicit $x10
112 regBankSelected: true
113 tracksRegLiveness: true
118 ; CHECK-LABEL: name: shl_add
119 ; CHECK: liveins: $x10, $x11
121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
123 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
124 ; CHECK-NEXT: $x10 = COPY [[SLL]]
125 ; CHECK-NEXT: PseudoRET implicit $x10
126 %0:gprb(s64) = COPY $x10
127 %1:gprb(s64) = COPY $x11
128 %2:gprb(s64) = G_CONSTANT i64 64
129 %3:gprb(s64) = G_ADD %1, %2
130 %4:gprb(s64) = G_SHL %0, %3(s64)
132 PseudoRET implicit $x10
138 regBankSelected: true
139 tracksRegLiveness: true
144 ; CHECK-LABEL: name: shl_sub
145 ; CHECK: liveins: $x10, $x11
147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
148 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
149 ; CHECK-NEXT: [[SUBW:%[0-9]+]]:gpr = SUBW $x0, [[COPY1]]
150 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUBW]]
151 ; CHECK-NEXT: $x10 = COPY [[SLL]]
152 ; CHECK-NEXT: PseudoRET implicit $x10
153 %0:gprb(s64) = COPY $x10
154 %1:gprb(s64) = COPY $x11
155 %2:gprb(s64) = G_CONSTANT i64 64
156 %3:gprb(s64) = G_SUB %2, %1
157 %4:gprb(s64) = G_SHL %0, %3(s64)
159 PseudoRET implicit $x10
163 name: shl_bitwise_not
165 regBankSelected: true
166 tracksRegLiveness: true
171 ; CHECK-LABEL: name: shl_bitwise_not
172 ; CHECK: liveins: $x10, $x11
174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
175 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
176 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
177 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]
178 ; CHECK-NEXT: $x10 = COPY [[SLL]]
179 ; CHECK-NEXT: PseudoRET implicit $x10
180 %0:gprb(s64) = COPY $x10
181 %1:gprb(s64) = COPY $x11
182 %2:gprb(s64) = G_CONSTANT i64 -1
183 %3:gprb(s64) = G_SUB %2, %1
184 %4:gprb(s64) = G_SHL %0, %3(s64)
186 PseudoRET implicit $x10
190 name: shl_bitwise_not_2
192 regBankSelected: true
193 tracksRegLiveness: true
198 ; CHECK-LABEL: name: shl_bitwise_not_2
199 ; CHECK: liveins: $x10, $x11
201 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
202 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
203 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
204 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]
205 ; CHECK-NEXT: $x10 = COPY [[SLL]]
206 ; CHECK-NEXT: PseudoRET implicit $x10
207 %0:gprb(s64) = COPY $x10
208 %1:gprb(s64) = COPY $x11
209 %2:gprb(s64) = G_CONSTANT i64 63
210 %3:gprb(s64) = G_SUB %2, %1
211 %4:gprb(s64) = G_SHL %0, %3(s64)
213 PseudoRET implicit $x10
219 regBankSelected: true
220 tracksRegLiveness: true
225 ; CHECK-LABEL: name: shl_and_zext
226 ; CHECK: liveins: $x10, $x11
228 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
229 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
230 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (load (s32))
231 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[LW]]
232 ; CHECK-NEXT: $x10 = COPY [[SLL]]
233 ; CHECK-NEXT: PseudoRET implicit $x10
234 %0:gprb(s64) = COPY $x10
235 %1:gprb(p0) = COPY $x11
236 %2:gprb(s32) = G_LOAD %1(p0) :: (load (s32))
237 %3:gprb(s32) = G_CONSTANT i32 63
238 %4:gprb(s32) = G_AND %2, %3
239 %5:gprb(s64) = G_ZEXT %4
240 %6:gprb(s64) = G_SHL %0, %5(s64)
242 PseudoRET implicit $x10
248 regBankSelected: true
249 tracksRegLiveness: true
254 ; CHECK-LABEL: name: srl_and_needed
255 ; CHECK: liveins: $x10, $x11
257 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
258 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
259 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15
260 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]
261 ; CHECK-NEXT: $x10 = COPY [[SRL]]
262 ; CHECK-NEXT: PseudoRET implicit $x10
263 %0:gprb(s64) = COPY $x10
264 %1:gprb(s64) = COPY $x11
265 %2:gprb(s32) = G_CONSTANT i32 15
266 %3:gprb(s32) = G_TRUNC %0(s64)
267 %4:gprb(s32) = G_AND %3, %2
268 %5:gprb(s64) = nneg G_ZEXT %4(s32)
269 %6:gprb(s64) = G_LSHR %1, %5(s64)
271 PseudoRET implicit $x10
275 name: srl_and_eliminated
277 regBankSelected: true
278 tracksRegLiveness: true
283 ; CHECK-LABEL: name: srl_and_eliminated
284 ; CHECK: liveins: $x10, $x11
286 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
287 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
288 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 79
289 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]
290 ; CHECK-NEXT: $x10 = COPY [[SRL]]
291 ; CHECK-NEXT: PseudoRET implicit $x10
292 %0:gprb(s64) = COPY $x10
293 %1:gprb(s64) = COPY $x11
294 %2:gprb(s32) = G_CONSTANT i32 15
295 %3:gprb(s32) = G_TRUNC %0(s64)
296 %7:gprb(s32) = G_CONSTANT i32 79
297 %8:gprb(s32) = G_AND %3, %7
298 %4:gprb(s32) = G_AND %8, %2
299 %5:gprb(s64) = nneg G_ZEXT %4(s32)
300 %6:gprb(s64) = G_LSHR %1, %5(s64)
302 PseudoRET implicit $x10