1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S | FileCheck %s
4 ; Regression test for a bug in the SLP vectorizer that was causing
5 ; these rotates to be incorrectly combined into a vector rotate.
7 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8 target triple = "wasm32-unknown-unknown"
10 define void @foo(<2 x i64> %x, <4 x i32> %y, ptr %out) #0 {
12 ; CHECK-NEXT: [[A:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
13 ; CHECK-NEXT: [[B:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 2
14 ; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[B]] to i64
15 ; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[A]], i64 [[A]], i64 [[CONV6]])
16 ; CHECK-NEXT: store i64 [[C]], ptr [[OUT:%.*]], align 8
17 ; CHECK-NEXT: [[D:%.*]] = extractelement <2 x i64> [[X]], i64 1
18 ; CHECK-NEXT: [[E:%.*]] = extractelement <4 x i32> [[Y]], i64 3
19 ; CHECK-NEXT: [[CONV17:%.*]] = zext i32 [[E]] to i64
20 ; CHECK-NEXT: [[F:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[D]], i64 [[D]], i64 [[CONV17]])
21 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i32 8
22 ; CHECK-NEXT: store i64 [[F]], ptr [[ARRAYIDX2]], align 8
23 ; CHECK-NEXT: ret void
25 %a = extractelement <2 x i64> %x, i32 0
26 %b = extractelement <4 x i32> %y, i32 2
27 %conv6 = zext i32 %b to i64
28 %c = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %conv6)
29 store i64 %c, ptr %out
30 %d = extractelement <2 x i64> %x, i32 1
31 %e = extractelement <4 x i32> %y, i32 3
32 %conv17 = zext i32 %e to i64
33 %f = tail call i64 @llvm.fshl.i64(i64 %d, i64 %d, i64 %conv17)
34 %arrayidx2 = getelementptr inbounds i64, ptr %out, i32 1
35 store i64 %f, ptr %arrayidx2
39 declare i64 @llvm.fshl.i64(i64, i64, i64)
41 attributes #0 = {"target-cpu"="generic" "target-features"="+simd128"}