Revert " [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432)"
[llvm-project.git] / llvm / lib / Target / ARC / ARCTargetMachine.cpp
blob5f021cf1f442ec1f6814add9baf03eaf12bfb1f6
1 //===- ARCTargetMachine.cpp - Define TargetMachine for ARC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
12 #include "ARCTargetMachine.h"
13 #include "ARC.h"
14 #include "ARCMachineFunctionInfo.h"
15 #include "ARCTargetTransformInfo.h"
16 #include "TargetInfo/ARCTargetInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/MC/TargetRegistry.h"
21 #include <optional>
23 using namespace llvm;
25 static Reloc::Model getRelocModel(std::optional<Reloc::Model> RM) {
26 return RM.value_or(Reloc::Static);
29 /// ARCTargetMachine ctor - Create an ILP32 architecture model
30 ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT,
31 StringRef CPU, StringRef FS,
32 const TargetOptions &Options,
33 std::optional<Reloc::Model> RM,
34 std::optional<CodeModel::Model> CM,
35 CodeGenOptLevel OL, bool JIT)
36 : LLVMTargetMachine(T,
37 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
38 "f32:32:32-i64:32-f64:32-a:0:32-n32",
39 TT, CPU, FS, Options, getRelocModel(RM),
40 getEffectiveCodeModel(CM, CodeModel::Small), OL),
41 TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
42 Subtarget(TT, std::string(CPU), std::string(FS), *this) {
43 initAsmInfo();
46 ARCTargetMachine::~ARCTargetMachine() = default;
48 namespace {
50 /// ARC Code Generator Pass Configuration Options.
51 class ARCPassConfig : public TargetPassConfig {
52 public:
53 ARCPassConfig(ARCTargetMachine &TM, PassManagerBase &PM)
54 : TargetPassConfig(TM, PM) {}
56 ARCTargetMachine &getARCTargetMachine() const {
57 return getTM<ARCTargetMachine>();
60 void addIRPasses() override;
61 bool addInstSelector() override;
62 void addPreEmitPass() override;
63 void addPreRegAlloc() override;
66 } // end anonymous namespace
68 TargetPassConfig *ARCTargetMachine::createPassConfig(PassManagerBase &PM) {
69 return new ARCPassConfig(*this, PM);
72 void ARCPassConfig::addIRPasses() {
73 addPass(createAtomicExpandLegacyPass());
75 TargetPassConfig::addIRPasses();
78 bool ARCPassConfig::addInstSelector() {
79 addPass(createARCISelDag(getARCTargetMachine(), getOptLevel()));
80 return false;
83 void ARCPassConfig::addPreEmitPass() { addPass(createARCBranchFinalizePass()); }
85 void ARCPassConfig::addPreRegAlloc() {
86 addPass(createARCExpandPseudosPass());
87 addPass(createARCOptAddrMode());
90 MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
91 BumpPtrAllocator &Allocator, const Function &F,
92 const TargetSubtargetInfo *STI) const {
93 return ARCFunctionInfo::create<ARCFunctionInfo>(Allocator, F, STI);
96 // Force static initialization.
97 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
98 RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
99 PassRegistry &PR = *PassRegistry::getPassRegistry();
100 initializeARCDAGToDAGISelLegacyPass(PR);
103 TargetTransformInfo
104 ARCTargetMachine::getTargetTransformInfo(const Function &F) const {
105 return TargetTransformInfo(ARCTTIImpl(this, F));