1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s | FileCheck %s
4 target triple = "aarch64-unknown-linux-gnu"
8 ; Tests adr z0.s, [z0.s, z0.s, lsl #<1,2,3>]
9 ; Other formats are tested in llvm/test/CodeGen/AArch64/sve-gep.ll
12 define <vscale x 4 x i32> @adr_32bit_lsl1(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
13 ; CHECK-LABEL: adr_32bit_lsl1:
15 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
17 %splat_insert = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
18 %one = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
19 %shiftedOffset = shl <vscale x 4 x i32> %idx, %one
20 %address = add <vscale x 4 x i32> %base, %shiftedOffset
21 ret <vscale x 4 x i32> %address
24 define <vscale x 4 x i32> @adr_32bit_lsl2(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
25 ; CHECK-LABEL: adr_32bit_lsl2:
27 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
29 %splat_insert = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
30 %two = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
31 %shiftedOffset = shl <vscale x 4 x i32> %idx, %two
32 %address = add <vscale x 4 x i32> %base, %shiftedOffset
33 ret <vscale x 4 x i32> %address
36 define <vscale x 4 x i32> @adr_32bit_lsl3(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
37 ; CHECK-LABEL: adr_32bit_lsl3:
39 ; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
41 %splat_insert = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
42 %three = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
43 %shiftedOffset = shl <vscale x 4 x i32> %idx, %three
44 %address = add <vscale x 4 x i32> %base, %shiftedOffset
45 ret <vscale x 4 x i32> %address
48 attributes #0 = { "target-features"="+sve" }