1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr8 < %s |\
3 ; RUN: FileCheck %s --check-prefix=32BIT
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64 -mcpu=pwr8 < %s |\
6 ; RUN: FileCheck %s --check-prefix=64BIT
8 define dso_local fastcc void @BuildVectorICE() unnamed_addr {
9 ; 32BIT-LABEL: BuildVectorICE:
10 ; 32BIT: # %bb.0: # %entry
11 ; 32BIT-NEXT: stwu 1, -64(1)
12 ; 32BIT-NEXT: .cfi_def_cfa_offset 64
13 ; 32BIT-NEXT: li 4, .LCPI0_0@l
14 ; 32BIT-NEXT: lis 5, .LCPI0_0@ha
15 ; 32BIT-NEXT: lxvw4x 34, 0, 3
17 ; 32BIT-NEXT: addi 6, 1, 48
19 ; 32BIT-NEXT: lxvw4x 35, 5, 4
20 ; 32BIT-NEXT: addi 4, 1, 32
21 ; 32BIT-NEXT: addi 5, 1, 16
22 ; 32BIT-NEXT: .p2align 4
23 ; 32BIT-NEXT: .LBB0_1: # %while.body
25 ; 32BIT-NEXT: stw 3, 32(1)
26 ; 32BIT-NEXT: stw 7, 16(1)
27 ; 32BIT-NEXT: lxvw4x 36, 0, 4
28 ; 32BIT-NEXT: lxvw4x 37, 0, 5
29 ; 32BIT-NEXT: vperm 4, 5, 4, 3
30 ; 32BIT-NEXT: vadduwm 4, 2, 4
31 ; 32BIT-NEXT: xxspltw 37, 36, 1
32 ; 32BIT-NEXT: vadduwm 4, 4, 5
33 ; 32BIT-NEXT: stxvw4x 36, 0, 6
34 ; 32BIT-NEXT: lwz 7, 48(1)
35 ; 32BIT-NEXT: b .LBB0_1
37 ; 64BIT-LABEL: BuildVectorICE:
38 ; 64BIT: # %bb.0: # %entry
39 ; 64BIT-NEXT: lxvw4x 34, 0, 3
41 ; 64BIT-NEXT: rldimi 3, 3, 32, 0
42 ; 64BIT-NEXT: mtfprd 0, 3
44 ; 64BIT-NEXT: .p2align 4
45 ; 64BIT-NEXT: .LBB0_1: # %while.body
48 ; 64BIT-NEXT: rldimi 4, 3, 32, 0
49 ; 64BIT-NEXT: mtfprd 1, 4
50 ; 64BIT-NEXT: xxmrghd 35, 1, 0
51 ; 64BIT-NEXT: vadduwm 3, 2, 3
52 ; 64BIT-NEXT: xxspltw 36, 35, 1
53 ; 64BIT-NEXT: vadduwm 3, 3, 4
54 ; 64BIT-NEXT: xxsldwi 1, 35, 35, 3
55 ; 64BIT-NEXT: mffprwz 3, 1
56 ; 64BIT-NEXT: b .LBB0_1
59 while.body: ; preds = %while.body, %entry
60 %newelement = phi i32 [ 0, %entry ], [ %5, %while.body ]
61 %0 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %newelement, i32 0
62 %1 = load <4 x i32>, ptr undef, align 1
63 %2 = add <4 x i32> %1, %0
64 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
65 %4 = add <4 x i32> %2, %3
66 %5 = extractelement <4 x i32> %4, i32 0