| blob | 00ca205e8597257273fed0bbc8988d9821664d33 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i32 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
16 ; CHECK-P8-NEXT: xxswapd vs0, v2
17 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
18 ; CHECK-P8-NEXT: mffprwz r3, f1
19 ; CHECK-P8-NEXT: mtvsrd v2, r3
20 ; CHECK-P8-NEXT: mffprwz r3, f0
21 ; CHECK-P8-NEXT: mtvsrd v3, r3
22 ; CHECK-P8-NEXT: vmrghh v2, v2, v3
23 ; CHECK-P8-NEXT: xxswapd vs0, v2
24 ; CHECK-P8-NEXT: mffprwz r3, f0
25 ; CHECK-P8-NEXT: blr
26 ;
27 ; CHECK-P9-LABEL: test2elt:
28 ; CHECK-P9: # %bb.0: # %entry
29 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
30 ; CHECK-P9-NEXT: mffprwz r3, f0
31 ; CHECK-P9-NEXT: xxswapd vs0, v2
32 ; CHECK-P9-NEXT: mtvsrd v3, r3
33 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
34 ; CHECK-P9-NEXT: mffprwz r3, f0
35 ; CHECK-P9-NEXT: mtvsrd v2, r3
36 ; CHECK-P9-NEXT: li r3, 0
37 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
38 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
39 ; CHECK-P9-NEXT: blr
40 ;
41 ; CHECK-BE-LABEL: test2elt:
42 ; CHECK-BE: # %bb.0: # %entry
43 ; CHECK-BE-NEXT: xxswapd vs2, v2
44 ; CHECK-BE-NEXT: xscvdpsxws f1, v2
45 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
46 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
47 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
48 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
49 ; CHECK-BE-NEXT: mffprwz r3, f1
50 ; CHECK-BE-NEXT: mtfprwz f1, r3
51 ; CHECK-BE-NEXT: mffprwz r3, f2
52 ; CHECK-BE-NEXT: mtvsrwz v2, r3
53 ; CHECK-BE-NEXT: li r3, 0
54 ; CHECK-BE-NEXT: xxperm v2, vs1, vs0
55 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
56 ; CHECK-BE-NEXT: blr
57 entry:
58 %0 = fptoui <2 x double> %a to <2 x i16>
59 %1 = bitcast <2 x i16> %0 to i32
60 ret i32 %1
61 }
63 define i64 @test4elt(ptr nocapture readonly) local_unnamed_addr #1 {
64 ; CHECK-P8-LABEL: test4elt:
65 ; CHECK-P8: # %bb.0: # %entry
66 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
67 ; CHECK-P8-NEXT: li r4, 16
68 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
69 ; CHECK-P8-NEXT: xxswapd vs1, vs0
70 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
71 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
72 ; CHECK-P8-NEXT: mffprwz r3, f0
73 ; CHECK-P8-NEXT: xscvdpsxws f0, f2
74 ; CHECK-P8-NEXT: mffprwz r4, f1
75 ; CHECK-P8-NEXT: mtvsrd v2, r3
76 ; CHECK-P8-NEXT: mtvsrd v3, r4
77 ; CHECK-P8-NEXT: xxswapd vs3, vs2
78 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
79 ; CHECK-P8-NEXT: mffprwz r3, f3
80 ; CHECK-P8-NEXT: mtvsrd v4, r3
81 ; CHECK-P8-NEXT: mffprwz r3, f0
82 ; CHECK-P8-NEXT: vmrghh v2, v3, v2
83 ; CHECK-P8-NEXT: mtvsrd v3, r3
84 ; CHECK-P8-NEXT: vmrghh v3, v4, v3
85 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
86 ; CHECK-P8-NEXT: xxswapd vs0, vs0
87 ; CHECK-P8-NEXT: mffprd r3, f0
88 ; CHECK-P8-NEXT: blr
89 ;
90 ; CHECK-P9-LABEL: test4elt:
91 ; CHECK-P9: # %bb.0: # %entry
92 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
93 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
94 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
95 ; CHECK-P9-NEXT: xxswapd vs1, vs1
96 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
97 ; CHECK-P9-NEXT: mffprwz r3, f2
98 ; CHECK-P9-NEXT: mtvsrd v2, r3
99 ; CHECK-P9-NEXT: mffprwz r3, f1
100 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
101 ; CHECK-P9-NEXT: xxswapd vs0, vs0
102 ; CHECK-P9-NEXT: mtvsrd v3, r3
103 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
104 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
105 ; CHECK-P9-NEXT: mffprwz r3, f1
106 ; CHECK-P9-NEXT: mtvsrd v3, r3
107 ; CHECK-P9-NEXT: mffprwz r3, f0
108 ; CHECK-P9-NEXT: mtvsrd v4, r3
109 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
110 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
111 ; CHECK-P9-NEXT: mfvsrld r3, vs0
112 ; CHECK-P9-NEXT: blr
113 ;
114 ; CHECK-BE-LABEL: test4elt:
115 ; CHECK-BE: # %bb.0: # %entry
116 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
117 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
118 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
119 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
120 ; CHECK-BE-NEXT: lxv vs2, 0(r3)
121 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
122 ; CHECK-BE-NEXT: xxswapd vs1, vs1
123 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
124 ; CHECK-BE-NEXT: mffprwz r3, f3
125 ; CHECK-BE-NEXT: mtfprwz f3, r3
126 ; CHECK-BE-NEXT: mffprwz r3, f1
127 ; CHECK-BE-NEXT: mtfprwz f1, r3
128 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs2
129 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
130 ; CHECK-BE-NEXT: xxswapd vs0, vs0
131 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
132 ; CHECK-BE-NEXT: mffprwz r3, f3
133 ; CHECK-BE-NEXT: mtfprwz f3, r3
134 ; CHECK-BE-NEXT: mffprwz r3, f0
135 ; CHECK-BE-NEXT: mtfprwz f0, r3
136 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs2
137 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
138 ; CHECK-BE-NEXT: mffprd r3, f0
139 ; CHECK-BE-NEXT: blr
140 entry:
141 %a = load <4 x double>, ptr %0, align 32
142 %1 = fptoui <4 x double> %a to <4 x i16>
143 %2 = bitcast <4 x i16> %1 to i64
144 ret i64 %2
145 }
147 define <8 x i16> @test8elt(ptr nocapture readonly) local_unnamed_addr #2 {
148 ; CHECK-P8-LABEL: test8elt:
149 ; CHECK-P8: # %bb.0: # %entry
150 ; CHECK-P8-NEXT: li r4, 16
151 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
152 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
153 ; CHECK-P8-NEXT: li r4, 32
154 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
155 ; CHECK-P8-NEXT: li r4, 48
156 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
157 ; CHECK-P8-NEXT: xxswapd vs3, vs1
158 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
159 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
160 ; CHECK-P8-NEXT: mffprwz r3, f1
161 ; CHECK-P8-NEXT: mtvsrd v2, r3
162 ; CHECK-P8-NEXT: xxswapd vs2, vs0
163 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
164 ; CHECK-P8-NEXT: mffprwz r4, f0
165 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
166 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
167 ; CHECK-P8-NEXT: mtvsrd v3, r4
168 ; CHECK-P8-NEXT: mffprwz r4, f3
169 ; CHECK-P8-NEXT: mtvsrd v5, r4
170 ; CHECK-P8-NEXT: xxswapd vs5, vs4
171 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
172 ; CHECK-P8-NEXT: mffprwz r3, f4
173 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
174 ; CHECK-P8-NEXT: mtvsrd v4, r3
175 ; CHECK-P8-NEXT: mffprwz r3, f2
176 ; CHECK-P8-NEXT: mffprwz r4, f5
177 ; CHECK-P8-NEXT: xxswapd vs7, vs6
178 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
179 ; CHECK-P8-NEXT: vmrghh v2, v5, v2
180 ; CHECK-P8-NEXT: mtvsrd v5, r3
181 ; CHECK-P8-NEXT: mffprwz r3, f7
182 ; CHECK-P8-NEXT: mtvsrd v0, r3
183 ; CHECK-P8-NEXT: mffprwz r3, f0
184 ; CHECK-P8-NEXT: vmrghh v3, v5, v3
185 ; CHECK-P8-NEXT: mtvsrd v5, r4
186 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
187 ; CHECK-P8-NEXT: vmrghh v4, v5, v4
188 ; CHECK-P8-NEXT: mtvsrd v5, r3
189 ; CHECK-P8-NEXT: vmrghh v5, v0, v5
190 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
191 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
192 ; CHECK-P8-NEXT: blr
193 ;
194 ; CHECK-P9-LABEL: test8elt:
195 ; CHECK-P9: # %bb.0: # %entry
196 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
197 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
198 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
199 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
200 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
201 ; CHECK-P9-NEXT: xxswapd vs3, vs3
202 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
203 ; CHECK-P9-NEXT: mffprwz r3, f4
204 ; CHECK-P9-NEXT: mtvsrd v2, r3
205 ; CHECK-P9-NEXT: mffprwz r3, f3
206 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
207 ; CHECK-P9-NEXT: xxswapd vs2, vs2
208 ; CHECK-P9-NEXT: mtvsrd v3, r3
209 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
210 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
211 ; CHECK-P9-NEXT: mffprwz r3, f3
212 ; CHECK-P9-NEXT: xscvdpsxws f3, f1
213 ; CHECK-P9-NEXT: xxswapd vs1, vs1
214 ; CHECK-P9-NEXT: mtvsrd v3, r3
215 ; CHECK-P9-NEXT: mffprwz r3, f2
216 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
217 ; CHECK-P9-NEXT: mtvsrd v4, r3
218 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
219 ; CHECK-P9-NEXT: mffprwz r3, f3
220 ; CHECK-P9-NEXT: xxmrglw vs2, v3, v2
221 ; CHECK-P9-NEXT: mtvsrd v2, r3
222 ; CHECK-P9-NEXT: mffprwz r3, f1
223 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
224 ; CHECK-P9-NEXT: xxswapd vs0, vs0
225 ; CHECK-P9-NEXT: mtvsrd v3, r3
226 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
227 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
228 ; CHECK-P9-NEXT: mffprwz r3, f1
229 ; CHECK-P9-NEXT: mtvsrd v3, r3
230 ; CHECK-P9-NEXT: mffprwz r3, f0
231 ; CHECK-P9-NEXT: mtvsrd v4, r3
232 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
233 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
234 ; CHECK-P9-NEXT: xxmrgld v2, vs0, vs2
235 ; CHECK-P9-NEXT: blr
236 ;
237 ; CHECK-BE-LABEL: test8elt:
238 ; CHECK-BE: # %bb.0: # %entry
239 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
240 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
241 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
242 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
243 ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
244 ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
245 ; CHECK-BE-NEXT: lxv vs4, 0(r3)
246 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
247 ; CHECK-BE-NEXT: xxswapd vs3, vs3
248 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
249 ; CHECK-BE-NEXT: mffprwz r3, f5
250 ; CHECK-BE-NEXT: mtfprwz f5, r3
251 ; CHECK-BE-NEXT: mffprwz r3, f3
252 ; CHECK-BE-NEXT: mtfprwz f3, r3
253 ; CHECK-BE-NEXT: xxperm vs3, vs5, vs4
254 ; CHECK-BE-NEXT: xscvdpsxws f5, f2
255 ; CHECK-BE-NEXT: xxswapd vs2, vs2
256 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
257 ; CHECK-BE-NEXT: mffprwz r3, f5
258 ; CHECK-BE-NEXT: mtfprwz f5, r3
259 ; CHECK-BE-NEXT: mffprwz r3, f2
260 ; CHECK-BE-NEXT: mtfprwz f2, r3
261 ; CHECK-BE-NEXT: xxperm vs2, vs5, vs4
262 ; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3
263 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
264 ; CHECK-BE-NEXT: xxswapd vs1, vs1
265 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
266 ; CHECK-BE-NEXT: mffprwz r3, f3
267 ; CHECK-BE-NEXT: mtfprwz f3, r3
268 ; CHECK-BE-NEXT: mffprwz r3, f1
269 ; CHECK-BE-NEXT: mtfprwz f1, r3
270 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs4
271 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
272 ; CHECK-BE-NEXT: xxswapd vs0, vs0
273 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
274 ; CHECK-BE-NEXT: mffprwz r3, f3
275 ; CHECK-BE-NEXT: mtfprwz f3, r3
276 ; CHECK-BE-NEXT: mffprwz r3, f0
277 ; CHECK-BE-NEXT: mtfprwz f0, r3
278 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs4
279 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
280 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2
281 ; CHECK-BE-NEXT: blr
282 entry:
283 %a = load <8 x double>, ptr %0, align 64
284 %1 = fptoui <8 x double> %a to <8 x i16>
285 ret <8 x i16> %1
286 }
288 define void @test16elt(ptr noalias nocapture sret(<16 x i16>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {
289 ; CHECK-P8-LABEL: test16elt:
290 ; CHECK-P8: # %bb.0: # %entry
291 ; CHECK-P8-NEXT: lxvd2x vs5, 0, r4
292 ; CHECK-P8-NEXT: li r5, 80
293 ; CHECK-P8-NEXT: li r6, 32
294 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r5
295 ; CHECK-P8-NEXT: li r5, 16
296 ; CHECK-P8-NEXT: lxvd2x vs9, r4, r6
297 ; CHECK-P8-NEXT: li r6, 64
298 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r5
299 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
300 ; CHECK-P8-NEXT: li r6, 48
301 ; CHECK-P8-NEXT: lxvd2x vs12, r4, r6
302 ; CHECK-P8-NEXT: li r6, 96
303 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
304 ; CHECK-P8-NEXT: li r6, 112
305 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
306 ; CHECK-P8-NEXT: xxswapd vs6, vs5
307 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
308 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
309 ; CHECK-P8-NEXT: mffprwz r4, f5
310 ; CHECK-P8-NEXT: mtvsrd v4, r4
311 ; CHECK-P8-NEXT: xxswapd vs10, vs9
312 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
313 ; CHECK-P8-NEXT: xxswapd vs4, vs3
314 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
315 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
316 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
317 ; CHECK-P8-NEXT: xxswapd vs8, vs7
318 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
319 ; CHECK-P8-NEXT: mffprwz r4, f7
320 ; CHECK-P8-NEXT: xxswapd vs13, vs11
321 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
322 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
323 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
324 ; CHECK-P8-NEXT: mtvsrd v5, r4
325 ; CHECK-P8-NEXT: xxswapd v2, vs12
326 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
327 ; CHECK-P8-NEXT: mffprwz r4, f9
328 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
329 ; CHECK-P8-NEXT: mtvsrd v0, r4
330 ; CHECK-P8-NEXT: mffprwz r4, f12
331 ; CHECK-P8-NEXT: mtvsrd v1, r4
332 ; CHECK-P8-NEXT: mffprwz r4, f11
333 ; CHECK-P8-NEXT: xxswapd v3, vs2
334 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
335 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
336 ; CHECK-P8-NEXT: mtvsrd v6, r4
337 ; CHECK-P8-NEXT: mffprwz r4, f3
338 ; CHECK-P8-NEXT: mtvsrd v7, r4
339 ; CHECK-P8-NEXT: mffprwz r4, f6
340 ; CHECK-P8-NEXT: mtvsrd v8, r4
341 ; CHECK-P8-NEXT: mffprwz r4, f8
342 ; CHECK-P8-NEXT: xxswapd vs1, vs0
343 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
344 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
345 ; CHECK-P8-NEXT: mtvsrd v9, r4
346 ; CHECK-P8-NEXT: mffprwz r4, f10
347 ; CHECK-P8-NEXT: mtvsrd v10, r4
348 ; CHECK-P8-NEXT: mfvsrwz r4, v2
349 ; CHECK-P8-NEXT: mtvsrd v2, r4
350 ; CHECK-P8-NEXT: mffprwz r4, f13
351 ; CHECK-P8-NEXT: vmrghh v4, v8, v4
352 ; CHECK-P8-NEXT: mtvsrd v8, r4
353 ; CHECK-P8-NEXT: mffprwz r4, f4
354 ; CHECK-P8-NEXT: vmrghh v5, v9, v5
355 ; CHECK-P8-NEXT: mtvsrd v9, r4
356 ; CHECK-P8-NEXT: mfvsrwz r4, v3
357 ; CHECK-P8-NEXT: vmrghh v0, v10, v0
358 ; CHECK-P8-NEXT: vmrghh v2, v2, v1
359 ; CHECK-P8-NEXT: vmrghh v3, v8, v6
360 ; CHECK-P8-NEXT: mtvsrd v6, r4
361 ; CHECK-P8-NEXT: mffprwz r4, f2
362 ; CHECK-P8-NEXT: vmrghh v1, v9, v7
363 ; CHECK-P8-NEXT: mtvsrd v7, r4
364 ; CHECK-P8-NEXT: mffprwz r4, f1
365 ; CHECK-P8-NEXT: xxmrglw vs2, v1, v3
366 ; CHECK-P8-NEXT: xxmrglw vs1, v2, v0
367 ; CHECK-P8-NEXT: vmrghh v6, v6, v7
368 ; CHECK-P8-NEXT: mtvsrd v7, r4
369 ; CHECK-P8-NEXT: mffprwz r4, f0
370 ; CHECK-P8-NEXT: xxmrglw vs0, v5, v4
371 ; CHECK-P8-NEXT: mtvsrd v8, r4
372 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
373 ; CHECK-P8-NEXT: xxswapd vs1, v2
374 ; CHECK-P8-NEXT: vmrghh v7, v7, v8
375 ; CHECK-P8-NEXT: xxmrglw vs3, v7, v6
376 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
377 ; CHECK-P8-NEXT: xxswapd vs0, v3
378 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
379 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
380 ; CHECK-P8-NEXT: blr
381 ;
382 ; CHECK-P9-LABEL: test16elt:
383 ; CHECK-P9: # %bb.0: # %entry
384 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
385 ; CHECK-P9-NEXT: lxv vs1, 16(r4)
386 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
387 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
388 ; CHECK-P9-NEXT: xscvdpsxws f4, f1
389 ; CHECK-P9-NEXT: xxswapd vs2, vs2
390 ; CHECK-P9-NEXT: xscvdpsxws f5, f0
391 ; CHECK-P9-NEXT: xxswapd vs1, vs1
392 ; CHECK-P9-NEXT: xxswapd vs0, vs0
393 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
394 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
395 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
396 ; CHECK-P9-NEXT: mffprwz r5, f3
397 ; CHECK-P9-NEXT: lxv vs3, 64(r4)
398 ; CHECK-P9-NEXT: mtvsrd v2, r5
399 ; CHECK-P9-NEXT: mffprwz r5, f4
400 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
401 ; CHECK-P9-NEXT: mtvsrd v3, r5
402 ; CHECK-P9-NEXT: mffprwz r5, f5
403 ; CHECK-P9-NEXT: xscvdpsxws f7, f3
404 ; CHECK-P9-NEXT: xxswapd vs3, vs3
405 ; CHECK-P9-NEXT: mtvsrd v4, r5
406 ; CHECK-P9-NEXT: mffprwz r5, f2
407 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
408 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
409 ; CHECK-P9-NEXT: xxswapd vs4, vs4
410 ; CHECK-P9-NEXT: mtvsrd v5, r5
411 ; CHECK-P9-NEXT: mffprwz r5, f1
412 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
413 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
414 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
415 ; CHECK-P9-NEXT: vmrghh v2, v2, v5
416 ; CHECK-P9-NEXT: mtvsrd v5, r5
417 ; CHECK-P9-NEXT: mffprwz r5, f0
418 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
419 ; CHECK-P9-NEXT: vmrghh v3, v3, v5
420 ; CHECK-P9-NEXT: mtvsrd v5, r5
421 ; CHECK-P9-NEXT: mffprwz r4, f5
422 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
423 ; CHECK-P9-NEXT: xxmrglw vs6, v3, v2
424 ; CHECK-P9-NEXT: mtvsrd v2, r4
425 ; CHECK-P9-NEXT: mffprwz r4, f4
426 ; CHECK-P9-NEXT: mtvsrd v3, r4
427 ; CHECK-P9-NEXT: mffprwz r4, f7
428 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
429 ; CHECK-P9-NEXT: mtvsrd v3, r4
430 ; CHECK-P9-NEXT: mffprwz r4, f3
431 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
432 ; CHECK-P9-NEXT: xxswapd vs2, vs2
433 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
434 ; CHECK-P9-NEXT: xxmrglw vs4, v2, v4
435 ; CHECK-P9-NEXT: mtvsrd v2, r4
436 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
437 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
438 ; CHECK-P9-NEXT: mffprwz r4, f3
439 ; CHECK-P9-NEXT: xscvdpsxws f3, f1
440 ; CHECK-P9-NEXT: xxswapd vs1, vs1
441 ; CHECK-P9-NEXT: mtvsrd v3, r4
442 ; CHECK-P9-NEXT: stxv vs4, 0(r3)
443 ; CHECK-P9-NEXT: mffprwz r4, f2
444 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
445 ; CHECK-P9-NEXT: mtvsrd v4, r4
446 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
447 ; CHECK-P9-NEXT: mffprwz r4, f3
448 ; CHECK-P9-NEXT: xxmrglw vs2, v3, v2
449 ; CHECK-P9-NEXT: mtvsrd v2, r4
450 ; CHECK-P9-NEXT: mffprwz r4, f1
451 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
452 ; CHECK-P9-NEXT: xxswapd vs0, vs0
453 ; CHECK-P9-NEXT: mtvsrd v3, r4
454 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
455 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
456 ; CHECK-P9-NEXT: mffprwz r4, f1
457 ; CHECK-P9-NEXT: mtvsrd v3, r4
458 ; CHECK-P9-NEXT: mffprwz r4, f0
459 ; CHECK-P9-NEXT: mtvsrd v4, r4
460 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
461 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
462 ; CHECK-P9-NEXT: xxmrgld vs0, vs0, vs2
463 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
464 ; CHECK-P9-NEXT: blr
465 ;
466 ; CHECK-BE-LABEL: test16elt:
467 ; CHECK-BE: # %bb.0: # %entry
468 ; CHECK-BE-NEXT: lxv vs7, 48(r4)
469 ; CHECK-BE-NEXT: lxv vs0, 64(r4)
470 ; CHECK-BE-NEXT: lxv vs1, 80(r4)
471 ; CHECK-BE-NEXT: lxv vs2, 96(r4)
472 ; CHECK-BE-NEXT: xscvdpsxws f9, f7
473 ; CHECK-BE-NEXT: xxswapd vs7, vs7
474 ; CHECK-BE-NEXT: lxv vs3, 112(r4)
475 ; CHECK-BE-NEXT: lxv vs4, 0(r4)
476 ; CHECK-BE-NEXT: lxv vs5, 16(r4)
477 ; CHECK-BE-NEXT: lxv vs6, 32(r4)
478 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
479 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
480 ; CHECK-BE-NEXT: lxv vs8, 0(r4)
481 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
482 ; CHECK-BE-NEXT: mffprwz r4, f9
483 ; CHECK-BE-NEXT: mtfprwz f9, r4
484 ; CHECK-BE-NEXT: mffprwz r4, f7
485 ; CHECK-BE-NEXT: mtfprwz f7, r4
486 ; CHECK-BE-NEXT: xxperm vs7, vs9, vs8
487 ; CHECK-BE-NEXT: xscvdpsxws f9, f6
488 ; CHECK-BE-NEXT: xxswapd vs6, vs6
489 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
490 ; CHECK-BE-NEXT: mffprwz r4, f9
491 ; CHECK-BE-NEXT: mtfprwz f9, r4
492 ; CHECK-BE-NEXT: mffprwz r4, f6
493 ; CHECK-BE-NEXT: mtfprwz f6, r4
494 ; CHECK-BE-NEXT: xxperm vs6, vs9, vs8
495 ; CHECK-BE-NEXT: xscvdpsxws f9, f5
496 ; CHECK-BE-NEXT: xxswapd vs5, vs5
497 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
498 ; CHECK-BE-NEXT: xxmrghw vs6, vs6, vs7
499 ; CHECK-BE-NEXT: mffprwz r4, f9
500 ; CHECK-BE-NEXT: mtfprwz f9, r4
501 ; CHECK-BE-NEXT: mffprwz r4, f5
502 ; CHECK-BE-NEXT: mtfprwz f5, r4
503 ; CHECK-BE-NEXT: xxperm vs5, vs9, vs8
504 ; CHECK-BE-NEXT: xscvdpsxws f9, f4
505 ; CHECK-BE-NEXT: xxswapd vs4, vs4
506 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
507 ; CHECK-BE-NEXT: mffprwz r4, f9
508 ; CHECK-BE-NEXT: mtfprwz f9, r4
509 ; CHECK-BE-NEXT: mffprwz r4, f4
510 ; CHECK-BE-NEXT: mtfprwz f4, r4
511 ; CHECK-BE-NEXT: xxperm vs4, vs9, vs8
512 ; CHECK-BE-NEXT: xscvdpsxws f9, f3
513 ; CHECK-BE-NEXT: xxswapd vs3, vs3
514 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
515 ; CHECK-BE-NEXT: xxmrghw vs4, vs4, vs5
516 ; CHECK-BE-NEXT: xscvdpsxws f5, f2
517 ; CHECK-BE-NEXT: xxswapd vs2, vs2
518 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
519 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
520 ; CHECK-BE-NEXT: mffprwz r4, f9
521 ; CHECK-BE-NEXT: mtfprwz f9, r4
522 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
523 ; CHECK-BE-NEXT: mffprwz r4, f3
524 ; CHECK-BE-NEXT: mtfprwz f3, r4
525 ; CHECK-BE-NEXT: mffprwz r4, f5
526 ; CHECK-BE-NEXT: mtfprwz f5, r4
527 ; CHECK-BE-NEXT: mffprwz r4, f2
528 ; CHECK-BE-NEXT: xxperm vs3, vs9, vs8
529 ; CHECK-BE-NEXT: mtfprwz f2, r4
530 ; CHECK-BE-NEXT: xxperm vs2, vs5, vs8
531 ; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3
532 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
533 ; CHECK-BE-NEXT: xxswapd vs1, vs1
534 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
535 ; CHECK-BE-NEXT: mffprwz r4, f3
536 ; CHECK-BE-NEXT: mtfprwz f3, r4
537 ; CHECK-BE-NEXT: mffprwz r4, f1
538 ; CHECK-BE-NEXT: mtfprwz f1, r4
539 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs8
540 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
541 ; CHECK-BE-NEXT: xxswapd vs0, vs0
542 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
543 ; CHECK-BE-NEXT: mffprwz r4, f3
544 ; CHECK-BE-NEXT: mtfprwz f3, r4
545 ; CHECK-BE-NEXT: mffprwz r4, f0
546 ; CHECK-BE-NEXT: mtfprwz f0, r4
547 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs8
548 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
549 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs2
550 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
551 ; CHECK-BE-NEXT: blr
552 entry:
553 %a = load <16 x double>, ptr %0, align 128
554 %1 = fptoui <16 x double> %a to <16 x i16>
555 store <16 x i16> %1, ptr %agg.result, align 32
556 ret void
557 }
559 define i32 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
560 ; CHECK-P8-LABEL: test2elt_signed:
561 ; CHECK-P8: # %bb.0: # %entry
562 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
563 ; CHECK-P8-NEXT: xxswapd vs0, v2
564 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
565 ; CHECK-P8-NEXT: mffprwz r3, f1
566 ; CHECK-P8-NEXT: mtvsrd v2, r3
567 ; CHECK-P8-NEXT: mffprwz r3, f0
568 ; CHECK-P8-NEXT: mtvsrd v3, r3
569 ; CHECK-P8-NEXT: vmrghh v2, v2, v3
570 ; CHECK-P8-NEXT: xxswapd vs0, v2
571 ; CHECK-P8-NEXT: mffprwz r3, f0
572 ; CHECK-P8-NEXT: blr
573 ;
574 ; CHECK-P9-LABEL: test2elt_signed:
575 ; CHECK-P9: # %bb.0: # %entry
576 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
577 ; CHECK-P9-NEXT: mffprwz r3, f0
578 ; CHECK-P9-NEXT: xxswapd vs0, v2
579 ; CHECK-P9-NEXT: mtvsrd v3, r3
580 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
581 ; CHECK-P9-NEXT: mffprwz r3, f0
582 ; CHECK-P9-NEXT: mtvsrd v2, r3
583 ; CHECK-P9-NEXT: li r3, 0
584 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
585 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
586 ; CHECK-P9-NEXT: blr
587 ;
588 ; CHECK-BE-LABEL: test2elt_signed:
589 ; CHECK-BE: # %bb.0: # %entry
590 ; CHECK-BE-NEXT: xxswapd vs2, v2
591 ; CHECK-BE-NEXT: xscvdpsxws f1, v2
592 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
593 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
594 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
595 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
596 ; CHECK-BE-NEXT: mffprwz r3, f1
597 ; CHECK-BE-NEXT: mtfprwz f1, r3
598 ; CHECK-BE-NEXT: mffprwz r3, f2
599 ; CHECK-BE-NEXT: mtvsrwz v2, r3
600 ; CHECK-BE-NEXT: li r3, 0
601 ; CHECK-BE-NEXT: xxperm v2, vs1, vs0
602 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
603 ; CHECK-BE-NEXT: blr
604 entry:
605 %0 = fptosi <2 x double> %a to <2 x i16>
606 %1 = bitcast <2 x i16> %0 to i32
607 ret i32 %1
608 }
610 define i64 @test4elt_signed(ptr nocapture readonly) local_unnamed_addr #1 {
611 ; CHECK-P8-LABEL: test4elt_signed:
612 ; CHECK-P8: # %bb.0: # %entry
613 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
614 ; CHECK-P8-NEXT: li r4, 16
615 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
616 ; CHECK-P8-NEXT: xxswapd vs1, vs0
617 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
618 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
619 ; CHECK-P8-NEXT: mffprwz r3, f0
620 ; CHECK-P8-NEXT: xscvdpsxws f0, f2
621 ; CHECK-P8-NEXT: mffprwz r4, f1
622 ; CHECK-P8-NEXT: mtvsrd v2, r3
623 ; CHECK-P8-NEXT: mtvsrd v3, r4
624 ; CHECK-P8-NEXT: xxswapd vs3, vs2
625 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
626 ; CHECK-P8-NEXT: mffprwz r3, f3
627 ; CHECK-P8-NEXT: mtvsrd v4, r3
628 ; CHECK-P8-NEXT: mffprwz r3, f0
629 ; CHECK-P8-NEXT: vmrghh v2, v3, v2
630 ; CHECK-P8-NEXT: mtvsrd v3, r3
631 ; CHECK-P8-NEXT: vmrghh v3, v4, v3
632 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
633 ; CHECK-P8-NEXT: xxswapd vs0, vs0
634 ; CHECK-P8-NEXT: mffprd r3, f0
635 ; CHECK-P8-NEXT: blr
636 ;
637 ; CHECK-P9-LABEL: test4elt_signed:
638 ; CHECK-P9: # %bb.0: # %entry
639 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
640 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
641 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
642 ; CHECK-P9-NEXT: xxswapd vs1, vs1
643 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
644 ; CHECK-P9-NEXT: mffprwz r3, f2
645 ; CHECK-P9-NEXT: mtvsrd v2, r3
646 ; CHECK-P9-NEXT: mffprwz r3, f1
647 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
648 ; CHECK-P9-NEXT: xxswapd vs0, vs0
649 ; CHECK-P9-NEXT: mtvsrd v3, r3
650 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
651 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
652 ; CHECK-P9-NEXT: mffprwz r3, f1
653 ; CHECK-P9-NEXT: mtvsrd v3, r3
654 ; CHECK-P9-NEXT: mffprwz r3, f0
655 ; CHECK-P9-NEXT: mtvsrd v4, r3
656 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
657 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
658 ; CHECK-P9-NEXT: mfvsrld r3, vs0
659 ; CHECK-P9-NEXT: blr
660 ;
661 ; CHECK-BE-LABEL: test4elt_signed:
662 ; CHECK-BE: # %bb.0: # %entry
663 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
664 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
665 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
666 ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
667 ; CHECK-BE-NEXT: lxv vs2, 0(r3)
668 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
669 ; CHECK-BE-NEXT: xxswapd vs1, vs1
670 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
671 ; CHECK-BE-NEXT: mffprwz r3, f3
672 ; CHECK-BE-NEXT: mtfprwz f3, r3
673 ; CHECK-BE-NEXT: mffprwz r3, f1
674 ; CHECK-BE-NEXT: mtfprwz f1, r3
675 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs2
676 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
677 ; CHECK-BE-NEXT: xxswapd vs0, vs0
678 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
679 ; CHECK-BE-NEXT: mffprwz r3, f3
680 ; CHECK-BE-NEXT: mtfprwz f3, r3
681 ; CHECK-BE-NEXT: mffprwz r3, f0
682 ; CHECK-BE-NEXT: mtfprwz f0, r3
683 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs2
684 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
685 ; CHECK-BE-NEXT: mffprd r3, f0
686 ; CHECK-BE-NEXT: blr
687 entry:
688 %a = load <4 x double>, ptr %0, align 32
689 %1 = fptosi <4 x double> %a to <4 x i16>
690 %2 = bitcast <4 x i16> %1 to i64
691 ret i64 %2
692 }
694 define <8 x i16> @test8elt_signed(ptr nocapture readonly) local_unnamed_addr #2 {
695 ; CHECK-P8-LABEL: test8elt_signed:
696 ; CHECK-P8: # %bb.0: # %entry
697 ; CHECK-P8-NEXT: li r4, 16
698 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
699 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
700 ; CHECK-P8-NEXT: li r4, 32
701 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
702 ; CHECK-P8-NEXT: li r4, 48
703 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
704 ; CHECK-P8-NEXT: xxswapd vs3, vs1
705 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
706 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
707 ; CHECK-P8-NEXT: mffprwz r3, f1
708 ; CHECK-P8-NEXT: mtvsrd v2, r3
709 ; CHECK-P8-NEXT: xxswapd vs2, vs0
710 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
711 ; CHECK-P8-NEXT: mffprwz r4, f0
712 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
713 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
714 ; CHECK-P8-NEXT: mtvsrd v3, r4
715 ; CHECK-P8-NEXT: mffprwz r4, f3
716 ; CHECK-P8-NEXT: mtvsrd v5, r4
717 ; CHECK-P8-NEXT: xxswapd vs5, vs4
718 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
719 ; CHECK-P8-NEXT: mffprwz r3, f4
720 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
721 ; CHECK-P8-NEXT: mtvsrd v4, r3
722 ; CHECK-P8-NEXT: mffprwz r3, f2
723 ; CHECK-P8-NEXT: mffprwz r4, f5
724 ; CHECK-P8-NEXT: xxswapd vs7, vs6
725 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
726 ; CHECK-P8-NEXT: vmrghh v2, v5, v2
727 ; CHECK-P8-NEXT: mtvsrd v5, r3
728 ; CHECK-P8-NEXT: mffprwz r3, f7
729 ; CHECK-P8-NEXT: mtvsrd v0, r3
730 ; CHECK-P8-NEXT: mffprwz r3, f0
731 ; CHECK-P8-NEXT: vmrghh v3, v5, v3
732 ; CHECK-P8-NEXT: mtvsrd v5, r4
733 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
734 ; CHECK-P8-NEXT: vmrghh v4, v5, v4
735 ; CHECK-P8-NEXT: mtvsrd v5, r3
736 ; CHECK-P8-NEXT: vmrghh v5, v0, v5
737 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v4
738 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
739 ; CHECK-P8-NEXT: blr
740 ;
741 ; CHECK-P9-LABEL: test8elt_signed:
742 ; CHECK-P9: # %bb.0: # %entry
743 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
744 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
745 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
746 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
747 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
748 ; CHECK-P9-NEXT: xxswapd vs3, vs3
749 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
750 ; CHECK-P9-NEXT: mffprwz r3, f4
751 ; CHECK-P9-NEXT: mtvsrd v2, r3
752 ; CHECK-P9-NEXT: mffprwz r3, f3
753 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
754 ; CHECK-P9-NEXT: xxswapd vs2, vs2
755 ; CHECK-P9-NEXT: mtvsrd v3, r3
756 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
757 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
758 ; CHECK-P9-NEXT: mffprwz r3, f3
759 ; CHECK-P9-NEXT: xscvdpsxws f3, f1
760 ; CHECK-P9-NEXT: xxswapd vs1, vs1
761 ; CHECK-P9-NEXT: mtvsrd v3, r3
762 ; CHECK-P9-NEXT: mffprwz r3, f2
763 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
764 ; CHECK-P9-NEXT: mtvsrd v4, r3
765 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
766 ; CHECK-P9-NEXT: mffprwz r3, f3
767 ; CHECK-P9-NEXT: xxmrglw vs2, v3, v2
768 ; CHECK-P9-NEXT: mtvsrd v2, r3
769 ; CHECK-P9-NEXT: mffprwz r3, f1
770 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
771 ; CHECK-P9-NEXT: xxswapd vs0, vs0
772 ; CHECK-P9-NEXT: mtvsrd v3, r3
773 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
774 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
775 ; CHECK-P9-NEXT: mffprwz r3, f1
776 ; CHECK-P9-NEXT: mtvsrd v3, r3
777 ; CHECK-P9-NEXT: mffprwz r3, f0
778 ; CHECK-P9-NEXT: mtvsrd v4, r3
779 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
780 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
781 ; CHECK-P9-NEXT: xxmrgld v2, vs0, vs2
782 ; CHECK-P9-NEXT: blr
783 ;
784 ; CHECK-BE-LABEL: test8elt_signed:
785 ; CHECK-BE: # %bb.0: # %entry
786 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
787 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
788 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
789 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
790 ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
791 ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l
792 ; CHECK-BE-NEXT: lxv vs4, 0(r3)
793 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
794 ; CHECK-BE-NEXT: xxswapd vs3, vs3
795 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
796 ; CHECK-BE-NEXT: mffprwz r3, f5
797 ; CHECK-BE-NEXT: mtfprwz f5, r3
798 ; CHECK-BE-NEXT: mffprwz r3, f3
799 ; CHECK-BE-NEXT: mtfprwz f3, r3
800 ; CHECK-BE-NEXT: xxperm vs3, vs5, vs4
801 ; CHECK-BE-NEXT: xscvdpsxws f5, f2
802 ; CHECK-BE-NEXT: xxswapd vs2, vs2
803 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
804 ; CHECK-BE-NEXT: mffprwz r3, f5
805 ; CHECK-BE-NEXT: mtfprwz f5, r3
806 ; CHECK-BE-NEXT: mffprwz r3, f2
807 ; CHECK-BE-NEXT: mtfprwz f2, r3
808 ; CHECK-BE-NEXT: xxperm vs2, vs5, vs4
809 ; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3
810 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
811 ; CHECK-BE-NEXT: xxswapd vs1, vs1
812 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
813 ; CHECK-BE-NEXT: mffprwz r3, f3
814 ; CHECK-BE-NEXT: mtfprwz f3, r3
815 ; CHECK-BE-NEXT: mffprwz r3, f1
816 ; CHECK-BE-NEXT: mtfprwz f1, r3
817 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs4
818 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
819 ; CHECK-BE-NEXT: xxswapd vs0, vs0
820 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
821 ; CHECK-BE-NEXT: mffprwz r3, f3
822 ; CHECK-BE-NEXT: mtfprwz f3, r3
823 ; CHECK-BE-NEXT: mffprwz r3, f0
824 ; CHECK-BE-NEXT: mtfprwz f0, r3
825 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs4
826 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
827 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2
828 ; CHECK-BE-NEXT: blr
829 entry:
830 %a = load <8 x double>, ptr %0, align 64
831 %1 = fptosi <8 x double> %a to <8 x i16>
832 ret <8 x i16> %1
833 }
835 define void @test16elt_signed(ptr noalias nocapture sret(<16 x i16>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {
836 ; CHECK-P8-LABEL: test16elt_signed:
837 ; CHECK-P8: # %bb.0: # %entry
838 ; CHECK-P8-NEXT: lxvd2x vs5, 0, r4
839 ; CHECK-P8-NEXT: li r5, 80
840 ; CHECK-P8-NEXT: li r6, 32
841 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r5
842 ; CHECK-P8-NEXT: li r5, 16
843 ; CHECK-P8-NEXT: lxvd2x vs9, r4, r6
844 ; CHECK-P8-NEXT: li r6, 64
845 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r5
846 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
847 ; CHECK-P8-NEXT: li r6, 48
848 ; CHECK-P8-NEXT: lxvd2x vs12, r4, r6
849 ; CHECK-P8-NEXT: li r6, 96
850 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
851 ; CHECK-P8-NEXT: li r6, 112
852 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
853 ; CHECK-P8-NEXT: xxswapd vs6, vs5
854 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
855 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
856 ; CHECK-P8-NEXT: mffprwz r4, f5
857 ; CHECK-P8-NEXT: mtvsrd v4, r4
858 ; CHECK-P8-NEXT: xxswapd vs10, vs9
859 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
860 ; CHECK-P8-NEXT: xxswapd vs4, vs3
861 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
862 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
863 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
864 ; CHECK-P8-NEXT: xxswapd vs8, vs7
865 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
866 ; CHECK-P8-NEXT: mffprwz r4, f7
867 ; CHECK-P8-NEXT: xxswapd vs13, vs11
868 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
869 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
870 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
871 ; CHECK-P8-NEXT: mtvsrd v5, r4
872 ; CHECK-P8-NEXT: xxswapd v2, vs12
873 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
874 ; CHECK-P8-NEXT: mffprwz r4, f9
875 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
876 ; CHECK-P8-NEXT: mtvsrd v0, r4
877 ; CHECK-P8-NEXT: mffprwz r4, f12
878 ; CHECK-P8-NEXT: mtvsrd v1, r4
879 ; CHECK-P8-NEXT: mffprwz r4, f11
880 ; CHECK-P8-NEXT: xxswapd v3, vs2
881 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
882 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
883 ; CHECK-P8-NEXT: mtvsrd v6, r4
884 ; CHECK-P8-NEXT: mffprwz r4, f3
885 ; CHECK-P8-NEXT: mtvsrd v7, r4
886 ; CHECK-P8-NEXT: mffprwz r4, f6
887 ; CHECK-P8-NEXT: mtvsrd v8, r4
888 ; CHECK-P8-NEXT: mffprwz r4, f8
889 ; CHECK-P8-NEXT: xxswapd vs1, vs0
890 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
891 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
892 ; CHECK-P8-NEXT: mtvsrd v9, r4
893 ; CHECK-P8-NEXT: mffprwz r4, f10
894 ; CHECK-P8-NEXT: mtvsrd v10, r4
895 ; CHECK-P8-NEXT: mfvsrwz r4, v2
896 ; CHECK-P8-NEXT: mtvsrd v2, r4
897 ; CHECK-P8-NEXT: mffprwz r4, f13
898 ; CHECK-P8-NEXT: vmrghh v4, v8, v4
899 ; CHECK-P8-NEXT: mtvsrd v8, r4
900 ; CHECK-P8-NEXT: mffprwz r4, f4
901 ; CHECK-P8-NEXT: vmrghh v5, v9, v5
902 ; CHECK-P8-NEXT: mtvsrd v9, r4
903 ; CHECK-P8-NEXT: mfvsrwz r4, v3
904 ; CHECK-P8-NEXT: vmrghh v0, v10, v0
905 ; CHECK-P8-NEXT: vmrghh v2, v2, v1
906 ; CHECK-P8-NEXT: vmrghh v3, v8, v6
907 ; CHECK-P8-NEXT: mtvsrd v6, r4
908 ; CHECK-P8-NEXT: mffprwz r4, f2
909 ; CHECK-P8-NEXT: vmrghh v1, v9, v7
910 ; CHECK-P8-NEXT: mtvsrd v7, r4
911 ; CHECK-P8-NEXT: mffprwz r4, f1
912 ; CHECK-P8-NEXT: xxmrglw vs2, v1, v3
913 ; CHECK-P8-NEXT: xxmrglw vs1, v2, v0
914 ; CHECK-P8-NEXT: vmrghh v6, v6, v7
915 ; CHECK-P8-NEXT: mtvsrd v7, r4
916 ; CHECK-P8-NEXT: mffprwz r4, f0
917 ; CHECK-P8-NEXT: xxmrglw vs0, v5, v4
918 ; CHECK-P8-NEXT: mtvsrd v8, r4
919 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
920 ; CHECK-P8-NEXT: xxswapd vs1, v2
921 ; CHECK-P8-NEXT: vmrghh v7, v7, v8
922 ; CHECK-P8-NEXT: xxmrglw vs3, v7, v6
923 ; CHECK-P8-NEXT: xxmrgld v3, vs3, vs2
924 ; CHECK-P8-NEXT: xxswapd vs0, v3
925 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
926 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
927 ; CHECK-P8-NEXT: blr
928 ;
929 ; CHECK-P9-LABEL: test16elt_signed:
930 ; CHECK-P9: # %bb.0: # %entry
931 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
932 ; CHECK-P9-NEXT: lxv vs1, 16(r4)
933 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
934 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
935 ; CHECK-P9-NEXT: xscvdpsxws f4, f1
936 ; CHECK-P9-NEXT: xxswapd vs2, vs2
937 ; CHECK-P9-NEXT: xscvdpsxws f5, f0
938 ; CHECK-P9-NEXT: xxswapd vs1, vs1
939 ; CHECK-P9-NEXT: xxswapd vs0, vs0
940 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
941 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
942 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
943 ; CHECK-P9-NEXT: mffprwz r5, f3
944 ; CHECK-P9-NEXT: lxv vs3, 64(r4)
945 ; CHECK-P9-NEXT: mtvsrd v2, r5
946 ; CHECK-P9-NEXT: mffprwz r5, f4
947 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
948 ; CHECK-P9-NEXT: mtvsrd v3, r5
949 ; CHECK-P9-NEXT: mffprwz r5, f5
950 ; CHECK-P9-NEXT: xscvdpsxws f7, f3
951 ; CHECK-P9-NEXT: xxswapd vs3, vs3
952 ; CHECK-P9-NEXT: mtvsrd v4, r5
953 ; CHECK-P9-NEXT: mffprwz r5, f2
954 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
955 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
956 ; CHECK-P9-NEXT: xxswapd vs4, vs4
957 ; CHECK-P9-NEXT: mtvsrd v5, r5
958 ; CHECK-P9-NEXT: mffprwz r5, f1
959 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
960 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
961 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
962 ; CHECK-P9-NEXT: vmrghh v2, v2, v5
963 ; CHECK-P9-NEXT: mtvsrd v5, r5
964 ; CHECK-P9-NEXT: mffprwz r5, f0
965 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
966 ; CHECK-P9-NEXT: vmrghh v3, v3, v5
967 ; CHECK-P9-NEXT: mtvsrd v5, r5
968 ; CHECK-P9-NEXT: mffprwz r4, f5
969 ; CHECK-P9-NEXT: vmrghh v4, v4, v5
970 ; CHECK-P9-NEXT: xxmrglw vs6, v3, v2
971 ; CHECK-P9-NEXT: mtvsrd v2, r4
972 ; CHECK-P9-NEXT: mffprwz r4, f4
973 ; CHECK-P9-NEXT: mtvsrd v3, r4
974 ; CHECK-P9-NEXT: mffprwz r4, f7
975 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
976 ; CHECK-P9-NEXT: mtvsrd v3, r4
977 ; CHECK-P9-NEXT: mffprwz r4, f3
978 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
979 ; CHECK-P9-NEXT: xxswapd vs2, vs2
980 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
981 ; CHECK-P9-NEXT: xxmrglw vs4, v2, v4
982 ; CHECK-P9-NEXT: mtvsrd v2, r4
983 ; CHECK-P9-NEXT: vmrghh v2, v3, v2
984 ; CHECK-P9-NEXT: xxmrgld vs4, vs4, vs6
985 ; CHECK-P9-NEXT: mffprwz r4, f3
986 ; CHECK-P9-NEXT: xscvdpsxws f3, f1
987 ; CHECK-P9-NEXT: xxswapd vs1, vs1
988 ; CHECK-P9-NEXT: mtvsrd v3, r4
989 ; CHECK-P9-NEXT: stxv vs4, 0(r3)
990 ; CHECK-P9-NEXT: mffprwz r4, f2
991 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
992 ; CHECK-P9-NEXT: mtvsrd v4, r4
993 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
994 ; CHECK-P9-NEXT: mffprwz r4, f3
995 ; CHECK-P9-NEXT: xxmrglw vs2, v3, v2
996 ; CHECK-P9-NEXT: mtvsrd v2, r4
997 ; CHECK-P9-NEXT: mffprwz r4, f1
998 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
999 ; CHECK-P9-NEXT: xxswapd vs0, vs0
1000 ; CHECK-P9-NEXT: mtvsrd v3, r4
1001 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
1002 ; CHECK-P9-NEXT: vmrghh v2, v2, v3
1003 ; CHECK-P9-NEXT: mffprwz r4, f1
1004 ; CHECK-P9-NEXT: mtvsrd v3, r4
1005 ; CHECK-P9-NEXT: mffprwz r4, f0
1006 ; CHECK-P9-NEXT: mtvsrd v4, r4
1007 ; CHECK-P9-NEXT: vmrghh v3, v3, v4
1008 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
1009 ; CHECK-P9-NEXT: xxmrgld vs0, vs0, vs2
1010 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
1011 ; CHECK-P9-NEXT: blr
1012 ;
1013 ; CHECK-BE-LABEL: test16elt_signed:
1014 ; CHECK-BE: # %bb.0: # %entry
1015 ; CHECK-BE-NEXT: lxv vs7, 48(r4)
1016 ; CHECK-BE-NEXT: lxv vs0, 64(r4)
1017 ; CHECK-BE-NEXT: lxv vs1, 80(r4)
1018 ; CHECK-BE-NEXT: lxv vs2, 96(r4)
1019 ; CHECK-BE-NEXT: xscvdpsxws f9, f7
1020 ; CHECK-BE-NEXT: xxswapd vs7, vs7
1021 ; CHECK-BE-NEXT: lxv vs3, 112(r4)
1022 ; CHECK-BE-NEXT: lxv vs4, 0(r4)
1023 ; CHECK-BE-NEXT: lxv vs5, 16(r4)
1024 ; CHECK-BE-NEXT: lxv vs6, 32(r4)
1025 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
1026 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
1027 ; CHECK-BE-NEXT: lxv vs8, 0(r4)
1028 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
1029 ; CHECK-BE-NEXT: mffprwz r4, f9
1030 ; CHECK-BE-NEXT: mtfprwz f9, r4
1031 ; CHECK-BE-NEXT: mffprwz r4, f7
1032 ; CHECK-BE-NEXT: mtfprwz f7, r4
1033 ; CHECK-BE-NEXT: xxperm vs7, vs9, vs8
1034 ; CHECK-BE-NEXT: xscvdpsxws f9, f6
1035 ; CHECK-BE-NEXT: xxswapd vs6, vs6
1036 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
1037 ; CHECK-BE-NEXT: mffprwz r4, f9
1038 ; CHECK-BE-NEXT: mtfprwz f9, r4
1039 ; CHECK-BE-NEXT: mffprwz r4, f6
1040 ; CHECK-BE-NEXT: mtfprwz f6, r4
1041 ; CHECK-BE-NEXT: xxperm vs6, vs9, vs8
1042 ; CHECK-BE-NEXT: xscvdpsxws f9, f5
1043 ; CHECK-BE-NEXT: xxswapd vs5, vs5
1044 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
1045 ; CHECK-BE-NEXT: xxmrghw vs6, vs6, vs7
1046 ; CHECK-BE-NEXT: mffprwz r4, f9
1047 ; CHECK-BE-NEXT: mtfprwz f9, r4
1048 ; CHECK-BE-NEXT: mffprwz r4, f5
1049 ; CHECK-BE-NEXT: mtfprwz f5, r4
1050 ; CHECK-BE-NEXT: xxperm vs5, vs9, vs8
1051 ; CHECK-BE-NEXT: xscvdpsxws f9, f4
1052 ; CHECK-BE-NEXT: xxswapd vs4, vs4
1053 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
1054 ; CHECK-BE-NEXT: mffprwz r4, f9
1055 ; CHECK-BE-NEXT: mtfprwz f9, r4
1056 ; CHECK-BE-NEXT: mffprwz r4, f4
1057 ; CHECK-BE-NEXT: mtfprwz f4, r4
1058 ; CHECK-BE-NEXT: xxperm vs4, vs9, vs8
1059 ; CHECK-BE-NEXT: xscvdpsxws f9, f3
1060 ; CHECK-BE-NEXT: xxswapd vs3, vs3
1061 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
1062 ; CHECK-BE-NEXT: xxmrghw vs4, vs4, vs5
1063 ; CHECK-BE-NEXT: xscvdpsxws f5, f2
1064 ; CHECK-BE-NEXT: xxswapd vs2, vs2
1065 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
1066 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
1067 ; CHECK-BE-NEXT: mffprwz r4, f9
1068 ; CHECK-BE-NEXT: mtfprwz f9, r4
1069 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
1070 ; CHECK-BE-NEXT: mffprwz r4, f3
1071 ; CHECK-BE-NEXT: mtfprwz f3, r4
1072 ; CHECK-BE-NEXT: mffprwz r4, f5
1073 ; CHECK-BE-NEXT: mtfprwz f5, r4
1074 ; CHECK-BE-NEXT: mffprwz r4, f2
1075 ; CHECK-BE-NEXT: xxperm vs3, vs9, vs8
1076 ; CHECK-BE-NEXT: mtfprwz f2, r4
1077 ; CHECK-BE-NEXT: xxperm vs2, vs5, vs8
1078 ; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3
1079 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
1080 ; CHECK-BE-NEXT: xxswapd vs1, vs1
1081 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
1082 ; CHECK-BE-NEXT: mffprwz r4, f3
1083 ; CHECK-BE-NEXT: mtfprwz f3, r4
1084 ; CHECK-BE-NEXT: mffprwz r4, f1
1085 ; CHECK-BE-NEXT: mtfprwz f1, r4
1086 ; CHECK-BE-NEXT: xxperm vs1, vs3, vs8
1087 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
1088 ; CHECK-BE-NEXT: xxswapd vs0, vs0
1089 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
1090 ; CHECK-BE-NEXT: mffprwz r4, f3
1091 ; CHECK-BE-NEXT: mtfprwz f3, r4
1092 ; CHECK-BE-NEXT: mffprwz r4, f0
1093 ; CHECK-BE-NEXT: mtfprwz f0, r4
1094 ; CHECK-BE-NEXT: xxperm vs0, vs3, vs8
1095 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1
1096 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs2
1097 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
1098 ; CHECK-BE-NEXT: blr
1099 entry:
1100 %a = load <16 x double>, ptr %0, align 128
1101 %1 = fptosi <16 x double> %a to <16 x i16>
1102 store <16 x i16> %1, ptr %agg.result, align 32
1103 ret void
1104 }