| blob | 770689ba98049b170ca404843d2d47716e0c2590 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i16 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
16 ; CHECK-P8-NEXT: xxswapd vs0, v2
17 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
18 ; CHECK-P8-NEXT: mffprwz r3, f1
19 ; CHECK-P8-NEXT: mtvsrd v2, r3
20 ; CHECK-P8-NEXT: mffprwz r3, f0
21 ; CHECK-P8-NEXT: mtvsrd v3, r3
22 ; CHECK-P8-NEXT: vmrghb v2, v2, v3
23 ; CHECK-P8-NEXT: xxswapd vs0, v2
24 ; CHECK-P8-NEXT: mffprd r3, f0
25 ; CHECK-P8-NEXT: clrldi r3, r3, 48
26 ; CHECK-P8-NEXT: sth r3, -2(r1)
27 ; CHECK-P8-NEXT: lhz r3, -2(r1)
28 ; CHECK-P8-NEXT: blr
29 ;
30 ; CHECK-P9-LABEL: test2elt:
31 ; CHECK-P9: # %bb.0: # %entry
32 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
33 ; CHECK-P9-NEXT: mffprwz r3, f0
34 ; CHECK-P9-NEXT: xxswapd vs0, v2
35 ; CHECK-P9-NEXT: mtvsrd v3, r3
36 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
37 ; CHECK-P9-NEXT: mffprwz r3, f0
38 ; CHECK-P9-NEXT: mtvsrd v2, r3
39 ; CHECK-P9-NEXT: addi r3, r1, -2
40 ; CHECK-P9-NEXT: vmrghb v2, v3, v2
41 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
42 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
43 ; CHECK-P9-NEXT: lhz r3, -2(r1)
44 ; CHECK-P9-NEXT: blr
45 ;
46 ; CHECK-BE-LABEL: test2elt:
47 ; CHECK-BE: # %bb.0: # %entry
48 ; CHECK-BE-NEXT: xxswapd vs2, v2
49 ; CHECK-BE-NEXT: xscvdpsxws f1, v2
50 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
51 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
52 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
53 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
54 ; CHECK-BE-NEXT: mffprwz r3, f1
55 ; CHECK-BE-NEXT: mtfprwz f1, r3
56 ; CHECK-BE-NEXT: mffprwz r3, f2
57 ; CHECK-BE-NEXT: mtvsrwz v2, r3
58 ; CHECK-BE-NEXT: addi r3, r1, -2
59 ; CHECK-BE-NEXT: xxperm v2, vs1, vs0
60 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
61 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
62 ; CHECK-BE-NEXT: lhz r3, -2(r1)
63 ; CHECK-BE-NEXT: blr
64 entry:
65 %0 = fptoui <2 x double> %a to <2 x i8>
66 %1 = bitcast <2 x i8> %0 to i16
67 ret i16 %1
68 }
70 define i32 @test4elt(ptr nocapture readonly) local_unnamed_addr #1 {
71 ; CHECK-P8-LABEL: test4elt:
72 ; CHECK-P8: # %bb.0: # %entry
73 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
74 ; CHECK-P8-NEXT: li r4, 16
75 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
76 ; CHECK-P8-NEXT: xxswapd vs1, vs0
77 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
78 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
79 ; CHECK-P8-NEXT: mffprwz r3, f0
80 ; CHECK-P8-NEXT: xscvdpsxws f0, f2
81 ; CHECK-P8-NEXT: mffprwz r4, f1
82 ; CHECK-P8-NEXT: mtvsrd v2, r3
83 ; CHECK-P8-NEXT: mtvsrd v3, r4
84 ; CHECK-P8-NEXT: xxswapd vs3, vs2
85 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
86 ; CHECK-P8-NEXT: mffprwz r3, f3
87 ; CHECK-P8-NEXT: mtvsrd v4, r3
88 ; CHECK-P8-NEXT: mffprwz r3, f0
89 ; CHECK-P8-NEXT: vmrghb v2, v3, v2
90 ; CHECK-P8-NEXT: mtvsrd v3, r3
91 ; CHECK-P8-NEXT: vmrghb v3, v4, v3
92 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
93 ; CHECK-P8-NEXT: xxswapd vs0, v2
94 ; CHECK-P8-NEXT: mffprwz r3, f0
95 ; CHECK-P8-NEXT: blr
96 ;
97 ; CHECK-P9-LABEL: test4elt:
98 ; CHECK-P9: # %bb.0: # %entry
99 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
100 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
101 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
102 ; CHECK-P9-NEXT: xxswapd vs1, vs1
103 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
104 ; CHECK-P9-NEXT: mffprwz r3, f2
105 ; CHECK-P9-NEXT: mtvsrd v2, r3
106 ; CHECK-P9-NEXT: mffprwz r3, f1
107 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
108 ; CHECK-P9-NEXT: xxswapd vs0, vs0
109 ; CHECK-P9-NEXT: mtvsrd v3, r3
110 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
111 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
112 ; CHECK-P9-NEXT: mffprwz r3, f1
113 ; CHECK-P9-NEXT: mtvsrd v3, r3
114 ; CHECK-P9-NEXT: mffprwz r3, f0
115 ; CHECK-P9-NEXT: mtvsrd v4, r3
116 ; CHECK-P9-NEXT: li r3, 0
117 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
118 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
119 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
120 ; CHECK-P9-NEXT: blr
121 ;
122 ; CHECK-BE-LABEL: test4elt:
123 ; CHECK-BE: # %bb.0: # %entry
124 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
125 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
126 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
127 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
128 ; CHECK-BE-NEXT: lxv vs2, 0(r3)
129 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
130 ; CHECK-BE-NEXT: xxswapd vs1, vs1
131 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
132 ; CHECK-BE-NEXT: mffprwz r3, f3
133 ; CHECK-BE-NEXT: mtfprwz f3, r3
134 ; CHECK-BE-NEXT: mffprwz r3, f1
135 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
136 ; CHECK-BE-NEXT: xxswapd vs0, vs0
137 ; CHECK-BE-NEXT: mtvsrwz v2, r3
138 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
139 ; CHECK-BE-NEXT: xxperm v2, vs3, vs2
140 ; CHECK-BE-NEXT: mffprwz r3, f1
141 ; CHECK-BE-NEXT: mtfprwz f1, r3
142 ; CHECK-BE-NEXT: mffprwz r3, f0
143 ; CHECK-BE-NEXT: mtvsrwz v3, r3
144 ; CHECK-BE-NEXT: li r3, 0
145 ; CHECK-BE-NEXT: xxperm v3, vs1, vs2
146 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
147 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
148 ; CHECK-BE-NEXT: blr
149 entry:
150 %a = load <4 x double>, ptr %0, align 32
151 %1 = fptoui <4 x double> %a to <4 x i8>
152 %2 = bitcast <4 x i8> %1 to i32
153 ret i32 %2
154 }
156 define i64 @test8elt(ptr nocapture readonly) local_unnamed_addr #1 {
157 ; CHECK-P8-LABEL: test8elt:
158 ; CHECK-P8: # %bb.0: # %entry
159 ; CHECK-P8-NEXT: li r4, 16
160 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
161 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
162 ; CHECK-P8-NEXT: li r4, 32
163 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
164 ; CHECK-P8-NEXT: li r4, 48
165 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
166 ; CHECK-P8-NEXT: xxswapd vs3, vs1
167 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
168 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
169 ; CHECK-P8-NEXT: mffprwz r3, f1
170 ; CHECK-P8-NEXT: mtvsrd v2, r3
171 ; CHECK-P8-NEXT: xxswapd vs2, vs0
172 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
173 ; CHECK-P8-NEXT: mffprwz r4, f0
174 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
175 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
176 ; CHECK-P8-NEXT: mtvsrd v3, r4
177 ; CHECK-P8-NEXT: mffprwz r4, f3
178 ; CHECK-P8-NEXT: mtvsrd v5, r4
179 ; CHECK-P8-NEXT: xxswapd vs5, vs4
180 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
181 ; CHECK-P8-NEXT: mffprwz r3, f4
182 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
183 ; CHECK-P8-NEXT: mtvsrd v4, r3
184 ; CHECK-P8-NEXT: mffprwz r3, f2
185 ; CHECK-P8-NEXT: mffprwz r4, f5
186 ; CHECK-P8-NEXT: xxswapd vs7, vs6
187 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
188 ; CHECK-P8-NEXT: vmrghb v2, v5, v2
189 ; CHECK-P8-NEXT: mtvsrd v5, r3
190 ; CHECK-P8-NEXT: mffprwz r3, f7
191 ; CHECK-P8-NEXT: mtvsrd v0, r3
192 ; CHECK-P8-NEXT: mffprwz r3, f0
193 ; CHECK-P8-NEXT: vmrghb v3, v5, v3
194 ; CHECK-P8-NEXT: mtvsrd v5, r4
195 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
196 ; CHECK-P8-NEXT: vmrghb v4, v5, v4
197 ; CHECK-P8-NEXT: mtvsrd v5, r3
198 ; CHECK-P8-NEXT: vmrghb v5, v0, v5
199 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
200 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
201 ; CHECK-P8-NEXT: xxswapd vs0, vs0
202 ; CHECK-P8-NEXT: mffprd r3, f0
203 ; CHECK-P8-NEXT: blr
204 ;
205 ; CHECK-P9-LABEL: test8elt:
206 ; CHECK-P9: # %bb.0: # %entry
207 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
208 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
209 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
210 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
211 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
212 ; CHECK-P9-NEXT: xxswapd vs3, vs3
213 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
214 ; CHECK-P9-NEXT: mffprwz r3, f4
215 ; CHECK-P9-NEXT: mtvsrd v2, r3
216 ; CHECK-P9-NEXT: mffprwz r3, f3
217 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
218 ; CHECK-P9-NEXT: xxswapd vs2, vs2
219 ; CHECK-P9-NEXT: mtvsrd v3, r3
220 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
221 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
222 ; CHECK-P9-NEXT: mffprwz r3, f3
223 ; CHECK-P9-NEXT: mtvsrd v3, r3
224 ; CHECK-P9-NEXT: mffprwz r3, f2
225 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
226 ; CHECK-P9-NEXT: xxswapd vs1, vs1
227 ; CHECK-P9-NEXT: mtvsrd v4, r3
228 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
229 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
230 ; CHECK-P9-NEXT: mffprwz r3, f2
231 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
232 ; CHECK-P9-NEXT: mtvsrd v3, r3
233 ; CHECK-P9-NEXT: mffprwz r3, f1
234 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
235 ; CHECK-P9-NEXT: xxswapd vs0, vs0
236 ; CHECK-P9-NEXT: mtvsrd v4, r3
237 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
238 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
239 ; CHECK-P9-NEXT: mffprwz r3, f1
240 ; CHECK-P9-NEXT: mtvsrd v4, r3
241 ; CHECK-P9-NEXT: mffprwz r3, f0
242 ; CHECK-P9-NEXT: mtvsrd v5, r3
243 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
244 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
245 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
246 ; CHECK-P9-NEXT: mfvsrld r3, vs0
247 ; CHECK-P9-NEXT: blr
248 ;
249 ; CHECK-BE-LABEL: test8elt:
250 ; CHECK-BE: # %bb.0: # %entry
251 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
252 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
253 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
254 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
255 ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
256 ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
257 ; CHECK-BE-NEXT: lxv vs4, 0(r3)
258 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
259 ; CHECK-BE-NEXT: xxswapd vs3, vs3
260 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
261 ; CHECK-BE-NEXT: mffprwz r3, f5
262 ; CHECK-BE-NEXT: mtfprwz f5, r3
263 ; CHECK-BE-NEXT: mffprwz r3, f3
264 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
265 ; CHECK-BE-NEXT: xxswapd vs2, vs2
266 ; CHECK-BE-NEXT: mtvsrwz v2, r3
267 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
268 ; CHECK-BE-NEXT: xxperm v2, vs5, vs4
269 ; CHECK-BE-NEXT: mffprwz r3, f3
270 ; CHECK-BE-NEXT: mtfprwz f3, r3
271 ; CHECK-BE-NEXT: mffprwz r3, f2
272 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
273 ; CHECK-BE-NEXT: xxswapd vs1, vs1
274 ; CHECK-BE-NEXT: mtvsrwz v3, r3
275 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
276 ; CHECK-BE-NEXT: xxperm v3, vs3, vs4
277 ; CHECK-BE-NEXT: mffprwz r3, f2
278 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
279 ; CHECK-BE-NEXT: mtfprwz f2, r3
280 ; CHECK-BE-NEXT: mffprwz r3, f1
281 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
282 ; CHECK-BE-NEXT: xxswapd vs0, vs0
283 ; CHECK-BE-NEXT: mtvsrwz v3, r3
284 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
285 ; CHECK-BE-NEXT: xxperm v3, vs2, vs4
286 ; CHECK-BE-NEXT: mffprwz r3, f1
287 ; CHECK-BE-NEXT: mtfprwz f1, r3
288 ; CHECK-BE-NEXT: mffprwz r3, f0
289 ; CHECK-BE-NEXT: mtvsrwz v4, r3
290 ; CHECK-BE-NEXT: xxperm v4, vs1, vs4
291 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
292 ; CHECK-BE-NEXT: xxmrghw vs0, v3, v2
293 ; CHECK-BE-NEXT: mffprd r3, f0
294 ; CHECK-BE-NEXT: blr
295 entry:
296 %a = load <8 x double>, ptr %0, align 64
297 %1 = fptoui <8 x double> %a to <8 x i8>
298 %2 = bitcast <8 x i8> %1 to i64
299 ret i64 %2
300 }
302 define <16 x i8> @test16elt(ptr nocapture readonly) local_unnamed_addr #2 {
303 ; CHECK-P8-LABEL: test16elt:
304 ; CHECK-P8: # %bb.0: # %entry
305 ; CHECK-P8-NEXT: li r4, 80
306 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r3
307 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
308 ; CHECK-P8-NEXT: li r4, 48
309 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
310 ; CHECK-P8-NEXT: li r4, 16
311 ; CHECK-P8-NEXT: lxvd2x vs7, r3, r4
312 ; CHECK-P8-NEXT: li r4, 32
313 ; CHECK-P8-NEXT: lxvd2x vs9, r3, r4
314 ; CHECK-P8-NEXT: li r4, 64
315 ; CHECK-P8-NEXT: lxvd2x vs12, r3, r4
316 ; CHECK-P8-NEXT: li r4, 96
317 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
318 ; CHECK-P8-NEXT: li r4, 112
319 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
320 ; CHECK-P8-NEXT: xxswapd vs5, vs4
321 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
322 ; CHECK-P8-NEXT: mffprwz r3, f4
323 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
324 ; CHECK-P8-NEXT: mtvsrd v4, r3
325 ; CHECK-P8-NEXT: xxswapd vs13, vs3
326 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
327 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
328 ; CHECK-P8-NEXT: xxswapd vs10, vs6
329 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
330 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
331 ; CHECK-P8-NEXT: xxswapd vs8, vs7
332 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
333 ; CHECK-P8-NEXT: mffprwz r4, f7
334 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
335 ; CHECK-P8-NEXT: mtvsrd v5, r4
336 ; CHECK-P8-NEXT: mffprwz r4, f6
337 ; CHECK-P8-NEXT: mtvsrd v1, r4
338 ; CHECK-P8-NEXT: mffprwz r4, f3
339 ; CHECK-P8-NEXT: xxswapd vs11, vs9
340 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
341 ; CHECK-P8-NEXT: mffprwz r3, f9
342 ; CHECK-P8-NEXT: mtvsrd v0, r3
343 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
344 ; CHECK-P8-NEXT: mtvsrd v7, r4
345 ; CHECK-P8-NEXT: mffprwz r4, f8
346 ; CHECK-P8-NEXT: mtvsrd v9, r4
347 ; CHECK-P8-NEXT: xxswapd v2, vs12
348 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
349 ; CHECK-P8-NEXT: mffprwz r3, f12
350 ; CHECK-P8-NEXT: mtvsrd v6, r3
351 ; CHECK-P8-NEXT: mffprwz r3, f5
352 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
353 ; CHECK-P8-NEXT: mtvsrd v8, r3
354 ; CHECK-P8-NEXT: mffprwz r3, f11
355 ; CHECK-P8-NEXT: xxswapd v3, vs2
356 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
357 ; CHECK-P8-NEXT: mffprwz r4, f10
358 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
359 ; CHECK-P8-NEXT: xxswapd vs1, vs0
360 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
361 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
362 ; CHECK-P8-NEXT: vmrghb v4, v8, v4
363 ; CHECK-P8-NEXT: mtvsrd v8, r3
364 ; CHECK-P8-NEXT: mfvsrwz r3, v2
365 ; CHECK-P8-NEXT: mtvsrd v2, r4
366 ; CHECK-P8-NEXT: mffprwz r4, f13
367 ; CHECK-P8-NEXT: vmrghb v5, v9, v5
368 ; CHECK-P8-NEXT: vmrghb v0, v8, v0
369 ; CHECK-P8-NEXT: mtvsrd v8, r3
370 ; CHECK-P8-NEXT: mfvsrwz r3, v3
371 ; CHECK-P8-NEXT: vmrglh v4, v5, v4
372 ; CHECK-P8-NEXT: mtvsrd v3, r4
373 ; CHECK-P8-NEXT: vmrghb v2, v2, v1
374 ; CHECK-P8-NEXT: vmrghb v1, v8, v6
375 ; CHECK-P8-NEXT: mtvsrd v6, r3
376 ; CHECK-P8-NEXT: mffprwz r3, f2
377 ; CHECK-P8-NEXT: vmrglh v2, v2, v0
378 ; CHECK-P8-NEXT: vmrghb v3, v3, v7
379 ; CHECK-P8-NEXT: mtvsrd v7, r3
380 ; CHECK-P8-NEXT: mffprwz r3, f1
381 ; CHECK-P8-NEXT: vmrglh v3, v3, v1
382 ; CHECK-P8-NEXT: vmrghb v6, v6, v7
383 ; CHECK-P8-NEXT: mtvsrd v7, r3
384 ; CHECK-P8-NEXT: mffprwz r3, f0
385 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v4
386 ; CHECK-P8-NEXT: mtvsrd v8, r3
387 ; CHECK-P8-NEXT: vmrghb v7, v7, v8
388 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
389 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v3
390 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
391 ; CHECK-P8-NEXT: blr
392 ;
393 ; CHECK-P9-LABEL: test16elt:
394 ; CHECK-P9: # %bb.0: # %entry
395 ; CHECK-P9-NEXT: lxv vs7, 0(r3)
396 ; CHECK-P9-NEXT: lxv vs6, 16(r3)
397 ; CHECK-P9-NEXT: lxv vs0, 112(r3)
398 ; CHECK-P9-NEXT: lxv vs1, 96(r3)
399 ; CHECK-P9-NEXT: xscvdpsxws f8, f7
400 ; CHECK-P9-NEXT: xxswapd vs7, vs7
401 ; CHECK-P9-NEXT: lxv vs2, 80(r3)
402 ; CHECK-P9-NEXT: lxv vs3, 64(r3)
403 ; CHECK-P9-NEXT: lxv vs4, 48(r3)
404 ; CHECK-P9-NEXT: lxv vs5, 32(r3)
405 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
406 ; CHECK-P9-NEXT: mffprwz r3, f8
407 ; CHECK-P9-NEXT: mtvsrd v2, r3
408 ; CHECK-P9-NEXT: mffprwz r3, f7
409 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
410 ; CHECK-P9-NEXT: xxswapd vs6, vs6
411 ; CHECK-P9-NEXT: mtvsrd v3, r3
412 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
413 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
414 ; CHECK-P9-NEXT: mffprwz r3, f7
415 ; CHECK-P9-NEXT: mtvsrd v3, r3
416 ; CHECK-P9-NEXT: mffprwz r3, f6
417 ; CHECK-P9-NEXT: xscvdpsxws f6, f5
418 ; CHECK-P9-NEXT: xxswapd vs5, vs5
419 ; CHECK-P9-NEXT: mtvsrd v4, r3
420 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
421 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
422 ; CHECK-P9-NEXT: mffprwz r3, f6
423 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
424 ; CHECK-P9-NEXT: mtvsrd v3, r3
425 ; CHECK-P9-NEXT: mffprwz r3, f5
426 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
427 ; CHECK-P9-NEXT: xxswapd vs4, vs4
428 ; CHECK-P9-NEXT: mtvsrd v4, r3
429 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
430 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
431 ; CHECK-P9-NEXT: mffprwz r3, f5
432 ; CHECK-P9-NEXT: xscvdpsxws f5, f3
433 ; CHECK-P9-NEXT: xxswapd vs3, vs3
434 ; CHECK-P9-NEXT: mtvsrd v4, r3
435 ; CHECK-P9-NEXT: mffprwz r3, f4
436 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
437 ; CHECK-P9-NEXT: mtvsrd v5, r3
438 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
439 ; CHECK-P9-NEXT: mffprwz r3, f5
440 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
441 ; CHECK-P9-NEXT: xxmrglw vs4, v3, v2
442 ; CHECK-P9-NEXT: mtvsrd v2, r3
443 ; CHECK-P9-NEXT: mffprwz r3, f3
444 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
445 ; CHECK-P9-NEXT: xxswapd vs2, vs2
446 ; CHECK-P9-NEXT: mtvsrd v3, r3
447 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
448 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
449 ; CHECK-P9-NEXT: mffprwz r3, f3
450 ; CHECK-P9-NEXT: mtvsrd v3, r3
451 ; CHECK-P9-NEXT: mffprwz r3, f2
452 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
453 ; CHECK-P9-NEXT: xxswapd vs1, vs1
454 ; CHECK-P9-NEXT: mtvsrd v4, r3
455 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
456 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
457 ; CHECK-P9-NEXT: mffprwz r3, f2
458 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
459 ; CHECK-P9-NEXT: mtvsrd v3, r3
460 ; CHECK-P9-NEXT: mffprwz r3, f1
461 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
462 ; CHECK-P9-NEXT: xxswapd vs0, vs0
463 ; CHECK-P9-NEXT: mtvsrd v4, r3
464 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
465 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
466 ; CHECK-P9-NEXT: mffprwz r3, f1
467 ; CHECK-P9-NEXT: mtvsrd v4, r3
468 ; CHECK-P9-NEXT: mffprwz r3, f0
469 ; CHECK-P9-NEXT: mtvsrd v5, r3
470 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
471 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
472 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
473 ; CHECK-P9-NEXT: xxmrgld v2, vs0, vs4
474 ; CHECK-P9-NEXT: blr
475 ;
476 ; CHECK-BE-LABEL: test16elt:
477 ; CHECK-BE: # %bb.0: # %entry
478 ; CHECK-BE-NEXT: lxv vs7, 112(r3)
479 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
480 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
481 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
482 ; CHECK-BE-NEXT: xscvdpsxws f9, f7
483 ; CHECK-BE-NEXT: xxswapd vs7, vs7
484 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
485 ; CHECK-BE-NEXT: lxv vs4, 64(r3)
486 ; CHECK-BE-NEXT: lxv vs5, 80(r3)
487 ; CHECK-BE-NEXT: lxv vs6, 96(r3)
488 ; CHECK-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
489 ; CHECK-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
490 ; CHECK-BE-NEXT: lxv vs8, 0(r3)
491 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
492 ; CHECK-BE-NEXT: mffprwz r3, f9
493 ; CHECK-BE-NEXT: mtfprwz f9, r3
494 ; CHECK-BE-NEXT: mffprwz r3, f7
495 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
496 ; CHECK-BE-NEXT: xxswapd vs6, vs6
497 ; CHECK-BE-NEXT: mtvsrwz v2, r3
498 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
499 ; CHECK-BE-NEXT: xxperm v2, vs9, vs8
500 ; CHECK-BE-NEXT: mffprwz r3, f7
501 ; CHECK-BE-NEXT: mtfprwz f7, r3
502 ; CHECK-BE-NEXT: mffprwz r3, f6
503 ; CHECK-BE-NEXT: xscvdpsxws f6, f5
504 ; CHECK-BE-NEXT: xxswapd vs5, vs5
505 ; CHECK-BE-NEXT: mtvsrwz v3, r3
506 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
507 ; CHECK-BE-NEXT: xxperm v3, vs7, vs8
508 ; CHECK-BE-NEXT: mffprwz r3, f6
509 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
510 ; CHECK-BE-NEXT: mtfprwz f6, r3
511 ; CHECK-BE-NEXT: mffprwz r3, f5
512 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
513 ; CHECK-BE-NEXT: xxswapd vs4, vs4
514 ; CHECK-BE-NEXT: mtvsrwz v3, r3
515 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
516 ; CHECK-BE-NEXT: xxperm v3, vs6, vs8
517 ; CHECK-BE-NEXT: mffprwz r3, f5
518 ; CHECK-BE-NEXT: mtfprwz f5, r3
519 ; CHECK-BE-NEXT: mffprwz r3, f4
520 ; CHECK-BE-NEXT: mtvsrwz v4, r3
521 ; CHECK-BE-NEXT: xxperm v4, vs5, vs8
522 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
523 ; CHECK-BE-NEXT: xxswapd vs3, vs3
524 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
525 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
526 ; CHECK-BE-NEXT: xxmrghw vs4, v3, v2
527 ; CHECK-BE-NEXT: mffprwz r3, f5
528 ; CHECK-BE-NEXT: mtfprwz f5, r3
529 ; CHECK-BE-NEXT: mffprwz r3, f3
530 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
531 ; CHECK-BE-NEXT: xxswapd vs2, vs2
532 ; CHECK-BE-NEXT: mtvsrwz v2, r3
533 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
534 ; CHECK-BE-NEXT: xxperm v2, vs5, vs8
535 ; CHECK-BE-NEXT: mffprwz r3, f3
536 ; CHECK-BE-NEXT: mtfprwz f3, r3
537 ; CHECK-BE-NEXT: mffprwz r3, f2
538 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
539 ; CHECK-BE-NEXT: xxswapd vs1, vs1
540 ; CHECK-BE-NEXT: mtvsrwz v3, r3
541 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
542 ; CHECK-BE-NEXT: xxperm v3, vs3, vs8
543 ; CHECK-BE-NEXT: mffprwz r3, f2
544 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
545 ; CHECK-BE-NEXT: mtfprwz f2, r3
546 ; CHECK-BE-NEXT: mffprwz r3, f1
547 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
548 ; CHECK-BE-NEXT: xxswapd vs0, vs0
549 ; CHECK-BE-NEXT: mtvsrwz v3, r3
550 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
551 ; CHECK-BE-NEXT: xxperm v3, vs2, vs8
552 ; CHECK-BE-NEXT: mffprwz r3, f1
553 ; CHECK-BE-NEXT: mtfprwz f1, r3
554 ; CHECK-BE-NEXT: mffprwz r3, f0
555 ; CHECK-BE-NEXT: mtvsrwz v4, r3
556 ; CHECK-BE-NEXT: xxperm v4, vs1, vs8
557 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
558 ; CHECK-BE-NEXT: xxmrghw vs0, v3, v2
559 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs4
560 ; CHECK-BE-NEXT: blr
561 entry:
562 %a = load <16 x double>, ptr %0, align 128
563 %1 = fptoui <16 x double> %a to <16 x i8>
564 ret <16 x i8> %1
565 }
567 define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
568 ; CHECK-P8-LABEL: test2elt_signed:
569 ; CHECK-P8: # %bb.0: # %entry
570 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
571 ; CHECK-P8-NEXT: xxswapd vs0, v2
572 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
573 ; CHECK-P8-NEXT: mffprwz r3, f1
574 ; CHECK-P8-NEXT: mtvsrd v2, r3
575 ; CHECK-P8-NEXT: mffprwz r3, f0
576 ; CHECK-P8-NEXT: mtvsrd v3, r3
577 ; CHECK-P8-NEXT: vmrghb v2, v2, v3
578 ; CHECK-P8-NEXT: xxswapd vs0, v2
579 ; CHECK-P8-NEXT: mffprd r3, f0
580 ; CHECK-P8-NEXT: clrldi r3, r3, 48
581 ; CHECK-P8-NEXT: sth r3, -2(r1)
582 ; CHECK-P8-NEXT: lhz r3, -2(r1)
583 ; CHECK-P8-NEXT: blr
584 ;
585 ; CHECK-P9-LABEL: test2elt_signed:
586 ; CHECK-P9: # %bb.0: # %entry
587 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
588 ; CHECK-P9-NEXT: mffprwz r3, f0
589 ; CHECK-P9-NEXT: xxswapd vs0, v2
590 ; CHECK-P9-NEXT: mtvsrd v3, r3
591 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
592 ; CHECK-P9-NEXT: mffprwz r3, f0
593 ; CHECK-P9-NEXT: mtvsrd v2, r3
594 ; CHECK-P9-NEXT: addi r3, r1, -2
595 ; CHECK-P9-NEXT: vmrghb v2, v3, v2
596 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
597 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
598 ; CHECK-P9-NEXT: lhz r3, -2(r1)
599 ; CHECK-P9-NEXT: blr
600 ;
601 ; CHECK-BE-LABEL: test2elt_signed:
602 ; CHECK-BE: # %bb.0: # %entry
603 ; CHECK-BE-NEXT: xxswapd vs2, v2
604 ; CHECK-BE-NEXT: xscvdpsxws f1, v2
605 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
606 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
607 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
608 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
609 ; CHECK-BE-NEXT: mffprwz r3, f1
610 ; CHECK-BE-NEXT: mtfprwz f1, r3
611 ; CHECK-BE-NEXT: mffprwz r3, f2
612 ; CHECK-BE-NEXT: mtvsrwz v2, r3
613 ; CHECK-BE-NEXT: addi r3, r1, -2
614 ; CHECK-BE-NEXT: xxperm v2, vs1, vs0
615 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
616 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
617 ; CHECK-BE-NEXT: lhz r3, -2(r1)
618 ; CHECK-BE-NEXT: blr
619 entry:
620 %0 = fptosi <2 x double> %a to <2 x i8>
621 %1 = bitcast <2 x i8> %0 to i16
622 ret i16 %1
623 }
625 define i32 @test4elt_signed(ptr nocapture readonly) local_unnamed_addr #1 {
626 ; CHECK-P8-LABEL: test4elt_signed:
627 ; CHECK-P8: # %bb.0: # %entry
628 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
629 ; CHECK-P8-NEXT: li r4, 16
630 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
631 ; CHECK-P8-NEXT: xxswapd vs1, vs0
632 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
633 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
634 ; CHECK-P8-NEXT: mffprwz r3, f0
635 ; CHECK-P8-NEXT: xscvdpsxws f0, f2
636 ; CHECK-P8-NEXT: mffprwz r4, f1
637 ; CHECK-P8-NEXT: mtvsrd v2, r3
638 ; CHECK-P8-NEXT: mtvsrd v3, r4
639 ; CHECK-P8-NEXT: xxswapd vs3, vs2
640 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
641 ; CHECK-P8-NEXT: mffprwz r3, f3
642 ; CHECK-P8-NEXT: mtvsrd v4, r3
643 ; CHECK-P8-NEXT: mffprwz r3, f0
644 ; CHECK-P8-NEXT: vmrghb v2, v3, v2
645 ; CHECK-P8-NEXT: mtvsrd v3, r3
646 ; CHECK-P8-NEXT: vmrghb v3, v4, v3
647 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
648 ; CHECK-P8-NEXT: xxswapd vs0, v2
649 ; CHECK-P8-NEXT: mffprwz r3, f0
650 ; CHECK-P8-NEXT: blr
651 ;
652 ; CHECK-P9-LABEL: test4elt_signed:
653 ; CHECK-P9: # %bb.0: # %entry
654 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
655 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
656 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
657 ; CHECK-P9-NEXT: xxswapd vs1, vs1
658 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
659 ; CHECK-P9-NEXT: mffprwz r3, f2
660 ; CHECK-P9-NEXT: mtvsrd v2, r3
661 ; CHECK-P9-NEXT: mffprwz r3, f1
662 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
663 ; CHECK-P9-NEXT: xxswapd vs0, vs0
664 ; CHECK-P9-NEXT: mtvsrd v3, r3
665 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
666 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
667 ; CHECK-P9-NEXT: mffprwz r3, f1
668 ; CHECK-P9-NEXT: mtvsrd v3, r3
669 ; CHECK-P9-NEXT: mffprwz r3, f0
670 ; CHECK-P9-NEXT: mtvsrd v4, r3
671 ; CHECK-P9-NEXT: li r3, 0
672 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
673 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
674 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
675 ; CHECK-P9-NEXT: blr
676 ;
677 ; CHECK-BE-LABEL: test4elt_signed:
678 ; CHECK-BE: # %bb.0: # %entry
679 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
680 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
681 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
682 ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
683 ; CHECK-BE-NEXT: lxv vs2, 0(r3)
684 ; CHECK-BE-NEXT: xscvdpsxws f3, f1
685 ; CHECK-BE-NEXT: xxswapd vs1, vs1
686 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
687 ; CHECK-BE-NEXT: mffprwz r3, f3
688 ; CHECK-BE-NEXT: mtfprwz f3, r3
689 ; CHECK-BE-NEXT: mffprwz r3, f1
690 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
691 ; CHECK-BE-NEXT: xxswapd vs0, vs0
692 ; CHECK-BE-NEXT: mtvsrwz v2, r3
693 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
694 ; CHECK-BE-NEXT: xxperm v2, vs3, vs2
695 ; CHECK-BE-NEXT: mffprwz r3, f1
696 ; CHECK-BE-NEXT: mtfprwz f1, r3
697 ; CHECK-BE-NEXT: mffprwz r3, f0
698 ; CHECK-BE-NEXT: mtvsrwz v3, r3
699 ; CHECK-BE-NEXT: li r3, 0
700 ; CHECK-BE-NEXT: xxperm v3, vs1, vs2
701 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
702 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
703 ; CHECK-BE-NEXT: blr
704 entry:
705 %a = load <4 x double>, ptr %0, align 32
706 %1 = fptosi <4 x double> %a to <4 x i8>
707 %2 = bitcast <4 x i8> %1 to i32
708 ret i32 %2
709 }
711 define i64 @test8elt_signed(ptr nocapture readonly) local_unnamed_addr #1 {
712 ; CHECK-P8-LABEL: test8elt_signed:
713 ; CHECK-P8: # %bb.0: # %entry
714 ; CHECK-P8-NEXT: li r4, 16
715 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
716 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
717 ; CHECK-P8-NEXT: li r4, 32
718 ; CHECK-P8-NEXT: lxvd2x vs4, r3, r4
719 ; CHECK-P8-NEXT: li r4, 48
720 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
721 ; CHECK-P8-NEXT: xxswapd vs3, vs1
722 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
723 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
724 ; CHECK-P8-NEXT: mffprwz r3, f1
725 ; CHECK-P8-NEXT: mtvsrd v2, r3
726 ; CHECK-P8-NEXT: xxswapd vs2, vs0
727 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
728 ; CHECK-P8-NEXT: mffprwz r4, f0
729 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
730 ; CHECK-P8-NEXT: xscvdpsxws f0, f6
731 ; CHECK-P8-NEXT: mtvsrd v3, r4
732 ; CHECK-P8-NEXT: mffprwz r4, f3
733 ; CHECK-P8-NEXT: mtvsrd v5, r4
734 ; CHECK-P8-NEXT: xxswapd vs5, vs4
735 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
736 ; CHECK-P8-NEXT: mffprwz r3, f4
737 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
738 ; CHECK-P8-NEXT: mtvsrd v4, r3
739 ; CHECK-P8-NEXT: mffprwz r3, f2
740 ; CHECK-P8-NEXT: mffprwz r4, f5
741 ; CHECK-P8-NEXT: xxswapd vs7, vs6
742 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
743 ; CHECK-P8-NEXT: vmrghb v2, v5, v2
744 ; CHECK-P8-NEXT: mtvsrd v5, r3
745 ; CHECK-P8-NEXT: mffprwz r3, f7
746 ; CHECK-P8-NEXT: mtvsrd v0, r3
747 ; CHECK-P8-NEXT: mffprwz r3, f0
748 ; CHECK-P8-NEXT: vmrghb v3, v5, v3
749 ; CHECK-P8-NEXT: mtvsrd v5, r4
750 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
751 ; CHECK-P8-NEXT: vmrghb v4, v5, v4
752 ; CHECK-P8-NEXT: mtvsrd v5, r3
753 ; CHECK-P8-NEXT: vmrghb v5, v0, v5
754 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
755 ; CHECK-P8-NEXT: xxmrglw vs0, v3, v2
756 ; CHECK-P8-NEXT: xxswapd vs0, vs0
757 ; CHECK-P8-NEXT: mffprd r3, f0
758 ; CHECK-P8-NEXT: blr
759 ;
760 ; CHECK-P9-LABEL: test8elt_signed:
761 ; CHECK-P9: # %bb.0: # %entry
762 ; CHECK-P9-NEXT: lxv vs3, 0(r3)
763 ; CHECK-P9-NEXT: lxv vs2, 16(r3)
764 ; CHECK-P9-NEXT: lxv vs0, 48(r3)
765 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
766 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
767 ; CHECK-P9-NEXT: xxswapd vs3, vs3
768 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
769 ; CHECK-P9-NEXT: mffprwz r3, f4
770 ; CHECK-P9-NEXT: mtvsrd v2, r3
771 ; CHECK-P9-NEXT: mffprwz r3, f3
772 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
773 ; CHECK-P9-NEXT: xxswapd vs2, vs2
774 ; CHECK-P9-NEXT: mtvsrd v3, r3
775 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
776 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
777 ; CHECK-P9-NEXT: mffprwz r3, f3
778 ; CHECK-P9-NEXT: mtvsrd v3, r3
779 ; CHECK-P9-NEXT: mffprwz r3, f2
780 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
781 ; CHECK-P9-NEXT: xxswapd vs1, vs1
782 ; CHECK-P9-NEXT: mtvsrd v4, r3
783 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
784 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
785 ; CHECK-P9-NEXT: mffprwz r3, f2
786 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
787 ; CHECK-P9-NEXT: mtvsrd v3, r3
788 ; CHECK-P9-NEXT: mffprwz r3, f1
789 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
790 ; CHECK-P9-NEXT: xxswapd vs0, vs0
791 ; CHECK-P9-NEXT: mtvsrd v4, r3
792 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
793 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
794 ; CHECK-P9-NEXT: mffprwz r3, f1
795 ; CHECK-P9-NEXT: mtvsrd v4, r3
796 ; CHECK-P9-NEXT: mffprwz r3, f0
797 ; CHECK-P9-NEXT: mtvsrd v5, r3
798 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
799 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
800 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
801 ; CHECK-P9-NEXT: mfvsrld r3, vs0
802 ; CHECK-P9-NEXT: blr
803 ;
804 ; CHECK-BE-LABEL: test8elt_signed:
805 ; CHECK-BE: # %bb.0: # %entry
806 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
807 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
808 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
809 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
810 ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
811 ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l
812 ; CHECK-BE-NEXT: lxv vs4, 0(r3)
813 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
814 ; CHECK-BE-NEXT: xxswapd vs3, vs3
815 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
816 ; CHECK-BE-NEXT: mffprwz r3, f5
817 ; CHECK-BE-NEXT: mtfprwz f5, r3
818 ; CHECK-BE-NEXT: mffprwz r3, f3
819 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
820 ; CHECK-BE-NEXT: xxswapd vs2, vs2
821 ; CHECK-BE-NEXT: mtvsrwz v2, r3
822 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
823 ; CHECK-BE-NEXT: xxperm v2, vs5, vs4
824 ; CHECK-BE-NEXT: mffprwz r3, f3
825 ; CHECK-BE-NEXT: mtfprwz f3, r3
826 ; CHECK-BE-NEXT: mffprwz r3, f2
827 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
828 ; CHECK-BE-NEXT: xxswapd vs1, vs1
829 ; CHECK-BE-NEXT: mtvsrwz v3, r3
830 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
831 ; CHECK-BE-NEXT: xxperm v3, vs3, vs4
832 ; CHECK-BE-NEXT: mffprwz r3, f2
833 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
834 ; CHECK-BE-NEXT: mtfprwz f2, r3
835 ; CHECK-BE-NEXT: mffprwz r3, f1
836 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
837 ; CHECK-BE-NEXT: xxswapd vs0, vs0
838 ; CHECK-BE-NEXT: mtvsrwz v3, r3
839 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
840 ; CHECK-BE-NEXT: xxperm v3, vs2, vs4
841 ; CHECK-BE-NEXT: mffprwz r3, f1
842 ; CHECK-BE-NEXT: mtfprwz f1, r3
843 ; CHECK-BE-NEXT: mffprwz r3, f0
844 ; CHECK-BE-NEXT: mtvsrwz v4, r3
845 ; CHECK-BE-NEXT: xxperm v4, vs1, vs4
846 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
847 ; CHECK-BE-NEXT: xxmrghw vs0, v3, v2
848 ; CHECK-BE-NEXT: mffprd r3, f0
849 ; CHECK-BE-NEXT: blr
850 entry:
851 %a = load <8 x double>, ptr %0, align 64
852 %1 = fptosi <8 x double> %a to <8 x i8>
853 %2 = bitcast <8 x i8> %1 to i64
854 ret i64 %2
855 }
857 define <16 x i8> @test16elt_signed(ptr nocapture readonly) local_unnamed_addr #2 {
858 ; CHECK-P8-LABEL: test16elt_signed:
859 ; CHECK-P8: # %bb.0: # %entry
860 ; CHECK-P8-NEXT: li r4, 80
861 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r3
862 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
863 ; CHECK-P8-NEXT: li r4, 48
864 ; CHECK-P8-NEXT: lxvd2x vs6, r3, r4
865 ; CHECK-P8-NEXT: li r4, 16
866 ; CHECK-P8-NEXT: lxvd2x vs7, r3, r4
867 ; CHECK-P8-NEXT: li r4, 32
868 ; CHECK-P8-NEXT: lxvd2x vs9, r3, r4
869 ; CHECK-P8-NEXT: li r4, 64
870 ; CHECK-P8-NEXT: lxvd2x vs12, r3, r4
871 ; CHECK-P8-NEXT: li r4, 96
872 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
873 ; CHECK-P8-NEXT: li r4, 112
874 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
875 ; CHECK-P8-NEXT: xxswapd vs5, vs4
876 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
877 ; CHECK-P8-NEXT: mffprwz r3, f4
878 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
879 ; CHECK-P8-NEXT: mtvsrd v4, r3
880 ; CHECK-P8-NEXT: xxswapd vs13, vs3
881 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
882 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
883 ; CHECK-P8-NEXT: xxswapd vs10, vs6
884 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
885 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
886 ; CHECK-P8-NEXT: xxswapd vs8, vs7
887 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
888 ; CHECK-P8-NEXT: mffprwz r4, f7
889 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
890 ; CHECK-P8-NEXT: mtvsrd v5, r4
891 ; CHECK-P8-NEXT: mffprwz r4, f6
892 ; CHECK-P8-NEXT: mtvsrd v1, r4
893 ; CHECK-P8-NEXT: mffprwz r4, f3
894 ; CHECK-P8-NEXT: xxswapd vs11, vs9
895 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
896 ; CHECK-P8-NEXT: mffprwz r3, f9
897 ; CHECK-P8-NEXT: mtvsrd v0, r3
898 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
899 ; CHECK-P8-NEXT: mtvsrd v7, r4
900 ; CHECK-P8-NEXT: mffprwz r4, f8
901 ; CHECK-P8-NEXT: mtvsrd v9, r4
902 ; CHECK-P8-NEXT: xxswapd v2, vs12
903 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
904 ; CHECK-P8-NEXT: mffprwz r3, f12
905 ; CHECK-P8-NEXT: mtvsrd v6, r3
906 ; CHECK-P8-NEXT: mffprwz r3, f5
907 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
908 ; CHECK-P8-NEXT: mtvsrd v8, r3
909 ; CHECK-P8-NEXT: mffprwz r3, f11
910 ; CHECK-P8-NEXT: xxswapd v3, vs2
911 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
912 ; CHECK-P8-NEXT: mffprwz r4, f10
913 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
914 ; CHECK-P8-NEXT: xxswapd vs1, vs0
915 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
916 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
917 ; CHECK-P8-NEXT: vmrghb v4, v8, v4
918 ; CHECK-P8-NEXT: mtvsrd v8, r3
919 ; CHECK-P8-NEXT: mfvsrwz r3, v2
920 ; CHECK-P8-NEXT: mtvsrd v2, r4
921 ; CHECK-P8-NEXT: mffprwz r4, f13
922 ; CHECK-P8-NEXT: vmrghb v5, v9, v5
923 ; CHECK-P8-NEXT: vmrghb v0, v8, v0
924 ; CHECK-P8-NEXT: mtvsrd v8, r3
925 ; CHECK-P8-NEXT: mfvsrwz r3, v3
926 ; CHECK-P8-NEXT: vmrglh v4, v5, v4
927 ; CHECK-P8-NEXT: mtvsrd v3, r4
928 ; CHECK-P8-NEXT: vmrghb v2, v2, v1
929 ; CHECK-P8-NEXT: vmrghb v1, v8, v6
930 ; CHECK-P8-NEXT: mtvsrd v6, r3
931 ; CHECK-P8-NEXT: mffprwz r3, f2
932 ; CHECK-P8-NEXT: vmrglh v2, v2, v0
933 ; CHECK-P8-NEXT: vmrghb v3, v3, v7
934 ; CHECK-P8-NEXT: mtvsrd v7, r3
935 ; CHECK-P8-NEXT: mffprwz r3, f1
936 ; CHECK-P8-NEXT: vmrglh v3, v3, v1
937 ; CHECK-P8-NEXT: vmrghb v6, v6, v7
938 ; CHECK-P8-NEXT: mtvsrd v7, r3
939 ; CHECK-P8-NEXT: mffprwz r3, f0
940 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v4
941 ; CHECK-P8-NEXT: mtvsrd v8, r3
942 ; CHECK-P8-NEXT: vmrghb v7, v7, v8
943 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
944 ; CHECK-P8-NEXT: xxmrglw vs1, v5, v3
945 ; CHECK-P8-NEXT: xxmrgld v2, vs1, vs0
946 ; CHECK-P8-NEXT: blr
947 ;
948 ; CHECK-P9-LABEL: test16elt_signed:
949 ; CHECK-P9: # %bb.0: # %entry
950 ; CHECK-P9-NEXT: lxv vs7, 0(r3)
951 ; CHECK-P9-NEXT: lxv vs6, 16(r3)
952 ; CHECK-P9-NEXT: lxv vs0, 112(r3)
953 ; CHECK-P9-NEXT: lxv vs1, 96(r3)
954 ; CHECK-P9-NEXT: xscvdpsxws f8, f7
955 ; CHECK-P9-NEXT: xxswapd vs7, vs7
956 ; CHECK-P9-NEXT: lxv vs2, 80(r3)
957 ; CHECK-P9-NEXT: lxv vs3, 64(r3)
958 ; CHECK-P9-NEXT: lxv vs4, 48(r3)
959 ; CHECK-P9-NEXT: lxv vs5, 32(r3)
960 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
961 ; CHECK-P9-NEXT: mffprwz r3, f8
962 ; CHECK-P9-NEXT: mtvsrd v2, r3
963 ; CHECK-P9-NEXT: mffprwz r3, f7
964 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
965 ; CHECK-P9-NEXT: xxswapd vs6, vs6
966 ; CHECK-P9-NEXT: mtvsrd v3, r3
967 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
968 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
969 ; CHECK-P9-NEXT: mffprwz r3, f7
970 ; CHECK-P9-NEXT: mtvsrd v3, r3
971 ; CHECK-P9-NEXT: mffprwz r3, f6
972 ; CHECK-P9-NEXT: xscvdpsxws f6, f5
973 ; CHECK-P9-NEXT: xxswapd vs5, vs5
974 ; CHECK-P9-NEXT: mtvsrd v4, r3
975 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
976 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
977 ; CHECK-P9-NEXT: mffprwz r3, f6
978 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
979 ; CHECK-P9-NEXT: mtvsrd v3, r3
980 ; CHECK-P9-NEXT: mffprwz r3, f5
981 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
982 ; CHECK-P9-NEXT: xxswapd vs4, vs4
983 ; CHECK-P9-NEXT: mtvsrd v4, r3
984 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
985 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
986 ; CHECK-P9-NEXT: mffprwz r3, f5
987 ; CHECK-P9-NEXT: xscvdpsxws f5, f3
988 ; CHECK-P9-NEXT: xxswapd vs3, vs3
989 ; CHECK-P9-NEXT: mtvsrd v4, r3
990 ; CHECK-P9-NEXT: mffprwz r3, f4
991 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
992 ; CHECK-P9-NEXT: mtvsrd v5, r3
993 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
994 ; CHECK-P9-NEXT: mffprwz r3, f5
995 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
996 ; CHECK-P9-NEXT: xxmrglw vs4, v3, v2
997 ; CHECK-P9-NEXT: mtvsrd v2, r3
998 ; CHECK-P9-NEXT: mffprwz r3, f3
999 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
1000 ; CHECK-P9-NEXT: xxswapd vs2, vs2
1001 ; CHECK-P9-NEXT: mtvsrd v3, r3
1002 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
1003 ; CHECK-P9-NEXT: vmrghb v2, v2, v3
1004 ; CHECK-P9-NEXT: mffprwz r3, f3
1005 ; CHECK-P9-NEXT: mtvsrd v3, r3
1006 ; CHECK-P9-NEXT: mffprwz r3, f2
1007 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
1008 ; CHECK-P9-NEXT: xxswapd vs1, vs1
1009 ; CHECK-P9-NEXT: mtvsrd v4, r3
1010 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
1011 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
1012 ; CHECK-P9-NEXT: mffprwz r3, f2
1013 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
1014 ; CHECK-P9-NEXT: mtvsrd v3, r3
1015 ; CHECK-P9-NEXT: mffprwz r3, f1
1016 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
1017 ; CHECK-P9-NEXT: xxswapd vs0, vs0
1018 ; CHECK-P9-NEXT: mtvsrd v4, r3
1019 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
1020 ; CHECK-P9-NEXT: vmrghb v3, v3, v4
1021 ; CHECK-P9-NEXT: mffprwz r3, f1
1022 ; CHECK-P9-NEXT: mtvsrd v4, r3
1023 ; CHECK-P9-NEXT: mffprwz r3, f0
1024 ; CHECK-P9-NEXT: mtvsrd v5, r3
1025 ; CHECK-P9-NEXT: vmrghb v4, v4, v5
1026 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
1027 ; CHECK-P9-NEXT: xxmrglw vs0, v3, v2
1028 ; CHECK-P9-NEXT: xxmrgld v2, vs0, vs4
1029 ; CHECK-P9-NEXT: blr
1030 ;
1031 ; CHECK-BE-LABEL: test16elt_signed:
1032 ; CHECK-BE: # %bb.0: # %entry
1033 ; CHECK-BE-NEXT: lxv vs7, 112(r3)
1034 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
1035 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
1036 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
1037 ; CHECK-BE-NEXT: xscvdpsxws f9, f7
1038 ; CHECK-BE-NEXT: xxswapd vs7, vs7
1039 ; CHECK-BE-NEXT: lxv vs3, 48(r3)
1040 ; CHECK-BE-NEXT: lxv vs4, 64(r3)
1041 ; CHECK-BE-NEXT: lxv vs5, 80(r3)
1042 ; CHECK-BE-NEXT: lxv vs6, 96(r3)
1043 ; CHECK-BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
1044 ; CHECK-BE-NEXT: addi r3, r3, .LCPI7_0@toc@l
1045 ; CHECK-BE-NEXT: lxv vs8, 0(r3)
1046 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
1047 ; CHECK-BE-NEXT: mffprwz r3, f9
1048 ; CHECK-BE-NEXT: mtfprwz f9, r3
1049 ; CHECK-BE-NEXT: mffprwz r3, f7
1050 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
1051 ; CHECK-BE-NEXT: xxswapd vs6, vs6
1052 ; CHECK-BE-NEXT: mtvsrwz v2, r3
1053 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
1054 ; CHECK-BE-NEXT: xxperm v2, vs9, vs8
1055 ; CHECK-BE-NEXT: mffprwz r3, f7
1056 ; CHECK-BE-NEXT: mtfprwz f7, r3
1057 ; CHECK-BE-NEXT: mffprwz r3, f6
1058 ; CHECK-BE-NEXT: xscvdpsxws f6, f5
1059 ; CHECK-BE-NEXT: xxswapd vs5, vs5
1060 ; CHECK-BE-NEXT: mtvsrwz v3, r3
1061 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
1062 ; CHECK-BE-NEXT: xxperm v3, vs7, vs8
1063 ; CHECK-BE-NEXT: mffprwz r3, f6
1064 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
1065 ; CHECK-BE-NEXT: mtfprwz f6, r3
1066 ; CHECK-BE-NEXT: mffprwz r3, f5
1067 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
1068 ; CHECK-BE-NEXT: xxswapd vs4, vs4
1069 ; CHECK-BE-NEXT: mtvsrwz v3, r3
1070 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
1071 ; CHECK-BE-NEXT: xxperm v3, vs6, vs8
1072 ; CHECK-BE-NEXT: mffprwz r3, f5
1073 ; CHECK-BE-NEXT: mtfprwz f5, r3
1074 ; CHECK-BE-NEXT: mffprwz r3, f4
1075 ; CHECK-BE-NEXT: mtvsrwz v4, r3
1076 ; CHECK-BE-NEXT: xxperm v4, vs5, vs8
1077 ; CHECK-BE-NEXT: xscvdpsxws f5, f3
1078 ; CHECK-BE-NEXT: xxswapd vs3, vs3
1079 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
1080 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
1081 ; CHECK-BE-NEXT: xxmrghw vs4, v3, v2
1082 ; CHECK-BE-NEXT: mffprwz r3, f5
1083 ; CHECK-BE-NEXT: mtfprwz f5, r3
1084 ; CHECK-BE-NEXT: mffprwz r3, f3
1085 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
1086 ; CHECK-BE-NEXT: xxswapd vs2, vs2
1087 ; CHECK-BE-NEXT: mtvsrwz v2, r3
1088 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
1089 ; CHECK-BE-NEXT: xxperm v2, vs5, vs8
1090 ; CHECK-BE-NEXT: mffprwz r3, f3
1091 ; CHECK-BE-NEXT: mtfprwz f3, r3
1092 ; CHECK-BE-NEXT: mffprwz r3, f2
1093 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
1094 ; CHECK-BE-NEXT: xxswapd vs1, vs1
1095 ; CHECK-BE-NEXT: mtvsrwz v3, r3
1096 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
1097 ; CHECK-BE-NEXT: xxperm v3, vs3, vs8
1098 ; CHECK-BE-NEXT: mffprwz r3, f2
1099 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
1100 ; CHECK-BE-NEXT: mtfprwz f2, r3
1101 ; CHECK-BE-NEXT: mffprwz r3, f1
1102 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
1103 ; CHECK-BE-NEXT: xxswapd vs0, vs0
1104 ; CHECK-BE-NEXT: mtvsrwz v3, r3
1105 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
1106 ; CHECK-BE-NEXT: xxperm v3, vs2, vs8
1107 ; CHECK-BE-NEXT: mffprwz r3, f1
1108 ; CHECK-BE-NEXT: mtfprwz f1, r3
1109 ; CHECK-BE-NEXT: mffprwz r3, f0
1110 ; CHECK-BE-NEXT: mtvsrwz v4, r3
1111 ; CHECK-BE-NEXT: xxperm v4, vs1, vs8
1112 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
1113 ; CHECK-BE-NEXT: xxmrghw vs0, v3, v2
1114 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs4
1115 ; CHECK-BE-NEXT: blr
1116 entry:
1117 %a = load <16 x double>, ptr %0, align 128
1118 %1 = fptosi <16 x double> %a to <16 x i8>
1119 ret <16 x i8> %1
1120 }