| blob | ce1e0c4711ffbe5fea4c0c1a2ad5d1221f70c1ae |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv32 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV32ZBB
6 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s -check-prefix=RV32XTHEADBB
8 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck %s -check-prefix=RV32XTHEADMAC
10 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
11 ; RUN: | FileCheck %s -check-prefix=RV32XTHEAD
12 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
13 ; RUN: | FileCheck %s -check-prefix=RV64I
14 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \
15 ; RUN: | FileCheck %s -check-prefix=RV64ZBB
16 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
17 ; RUN: | FileCheck %s -check-prefix=RV64XTHEADMAC
18 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
19 ; RUN: | FileCheck %s -check-prefix=RV64XTHEADBB
20 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
21 ; RUN: | FileCheck %s -check-prefix=RV64XTHEAD
23 define i32 @f(i32 %A, i32 %B, i32 %C) {
24 ; RV32I-LABEL: f:
25 ; RV32I: # %bb.0: # %entry
26 ; RV32I-NEXT: mul a0, a1, a0
27 ; RV32I-NEXT: slli a1, a0, 26
28 ; RV32I-NEXT: srli a1, a1, 28
29 ; RV32I-NEXT: slli a0, a0, 20
30 ; RV32I-NEXT: srli a0, a0, 25
31 ; RV32I-NEXT: mul a0, a1, a0
32 ; RV32I-NEXT: add a0, a0, a2
33 ; RV32I-NEXT: ret
34 ;
35 ; RV32ZBB-LABEL: f:
36 ; RV32ZBB: # %bb.0: # %entry
37 ; RV32ZBB-NEXT: mul a0, a1, a0
38 ; RV32ZBB-NEXT: slli a1, a0, 26
39 ; RV32ZBB-NEXT: srli a1, a1, 28
40 ; RV32ZBB-NEXT: slli a0, a0, 20
41 ; RV32ZBB-NEXT: srli a0, a0, 25
42 ; RV32ZBB-NEXT: mul a0, a1, a0
43 ; RV32ZBB-NEXT: add a0, a0, a2
44 ; RV32ZBB-NEXT: ret
45 ;
46 ; RV32XTHEADBB-LABEL: f:
47 ; RV32XTHEADBB: # %bb.0: # %entry
48 ; RV32XTHEADBB-NEXT: mul a0, a1, a0
49 ; RV32XTHEADBB-NEXT: th.extu a1, a0, 5, 2
50 ; RV32XTHEADBB-NEXT: th.extu a0, a0, 11, 5
51 ; RV32XTHEADBB-NEXT: mul a0, a1, a0
52 ; RV32XTHEADBB-NEXT: add a0, a0, a2
53 ; RV32XTHEADBB-NEXT: ret
54 ;
55 ; RV32XTHEADMAC-LABEL: f:
56 ; RV32XTHEADMAC: # %bb.0: # %entry
57 ; RV32XTHEADMAC-NEXT: mul a0, a1, a0
58 ; RV32XTHEADMAC-NEXT: slli a1, a0, 26
59 ; RV32XTHEADMAC-NEXT: srli a1, a1, 28
60 ; RV32XTHEADMAC-NEXT: slli a0, a0, 20
61 ; RV32XTHEADMAC-NEXT: srli a0, a0, 25
62 ; RV32XTHEADMAC-NEXT: th.mulah a2, a1, a0
63 ; RV32XTHEADMAC-NEXT: mv a0, a2
64 ; RV32XTHEADMAC-NEXT: ret
65 ;
66 ; RV32XTHEAD-LABEL: f:
67 ; RV32XTHEAD: # %bb.0: # %entry
68 ; RV32XTHEAD-NEXT: mul a0, a1, a0
69 ; RV32XTHEAD-NEXT: th.extu a1, a0, 5, 2
70 ; RV32XTHEAD-NEXT: th.extu a0, a0, 11, 5
71 ; RV32XTHEAD-NEXT: th.mulah a2, a1, a0
72 ; RV32XTHEAD-NEXT: mv a0, a2
73 ; RV32XTHEAD-NEXT: ret
74 ;
75 ; RV64I-LABEL: f:
76 ; RV64I: # %bb.0: # %entry
77 ; RV64I-NEXT: mul a0, a1, a0
78 ; RV64I-NEXT: slli a1, a0, 58
79 ; RV64I-NEXT: srli a1, a1, 60
80 ; RV64I-NEXT: slli a0, a0, 52
81 ; RV64I-NEXT: srli a0, a0, 57
82 ; RV64I-NEXT: mul a0, a1, a0
83 ; RV64I-NEXT: addw a0, a0, a2
84 ; RV64I-NEXT: ret
85 ;
86 ; RV64ZBB-LABEL: f:
87 ; RV64ZBB: # %bb.0: # %entry
88 ; RV64ZBB-NEXT: mul a0, a1, a0
89 ; RV64ZBB-NEXT: slli a1, a0, 58
90 ; RV64ZBB-NEXT: srli a1, a1, 60
91 ; RV64ZBB-NEXT: slli a0, a0, 52
92 ; RV64ZBB-NEXT: srli a0, a0, 57
93 ; RV64ZBB-NEXT: mul a0, a1, a0
94 ; RV64ZBB-NEXT: addw a0, a0, a2
95 ; RV64ZBB-NEXT: ret
96 ;
97 ; RV64XTHEADMAC-LABEL: f:
98 ; RV64XTHEADMAC: # %bb.0: # %entry
99 ; RV64XTHEADMAC-NEXT: mul a0, a1, a0
100 ; RV64XTHEADMAC-NEXT: slli a1, a0, 58
101 ; RV64XTHEADMAC-NEXT: srli a1, a1, 60
102 ; RV64XTHEADMAC-NEXT: slli a0, a0, 52
103 ; RV64XTHEADMAC-NEXT: srli a0, a0, 57
104 ; RV64XTHEADMAC-NEXT: th.mulah a2, a1, a0
105 ; RV64XTHEADMAC-NEXT: mv a0, a2
106 ; RV64XTHEADMAC-NEXT: ret
107 ;
108 ; RV64XTHEADBB-LABEL: f:
109 ; RV64XTHEADBB: # %bb.0: # %entry
110 ; RV64XTHEADBB-NEXT: mul a0, a1, a0
111 ; RV64XTHEADBB-NEXT: th.extu a1, a0, 5, 2
112 ; RV64XTHEADBB-NEXT: th.extu a0, a0, 11, 5
113 ; RV64XTHEADBB-NEXT: mul a0, a1, a0
114 ; RV64XTHEADBB-NEXT: addw a0, a0, a2
115 ; RV64XTHEADBB-NEXT: ret
116 ;
117 ; RV64XTHEAD-LABEL: f:
118 ; RV64XTHEAD: # %bb.0: # %entry
119 ; RV64XTHEAD-NEXT: mul a0, a1, a0
120 ; RV64XTHEAD-NEXT: th.extu a1, a0, 5, 2
121 ; RV64XTHEAD-NEXT: th.extu a0, a0, 11, 5
122 ; RV64XTHEAD-NEXT: th.mulah a2, a1, a0
123 ; RV64XTHEAD-NEXT: mv a0, a2
124 ; RV64XTHEAD-NEXT: ret
125 entry:
126 %mul = mul nsw i32 %B, %A
127 %0 = lshr i32 %mul, 2
128 %and = and i32 %0, 15
129 %1 = lshr i32 %mul, 5
130 %and2 = and i32 %1, 127
131 %mul3 = mul nuw nsw i32 %and, %and2
132 %add = add i32 %mul3, %C
133 ret i32 %add
134 }