| blob | 31e25702da8ba273dbc332d0dd7b41820c364b72 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefixes=RV32I %s
4 ; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefixes=RV64I %s
7 define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
8 ; RV32I-LABEL: foo:
9 ; RV32I: # %bb.0:
10 ; RV32I-NEXT: lw a2, 0(a1)
11 ; RV32I-NEXT: beq a0, a2, .LBB0_2
12 ; RV32I-NEXT: # %bb.1:
13 ; RV32I-NEXT: mv a0, a2
14 ; RV32I-NEXT: .LBB0_2:
15 ; RV32I-NEXT: lw a2, 0(a1)
16 ; RV32I-NEXT: bne a0, a2, .LBB0_4
17 ; RV32I-NEXT: # %bb.3:
18 ; RV32I-NEXT: mv a0, a2
19 ; RV32I-NEXT: .LBB0_4:
20 ; RV32I-NEXT: lw a2, 0(a1)
21 ; RV32I-NEXT: bltu a2, a0, .LBB0_6
22 ; RV32I-NEXT: # %bb.5:
23 ; RV32I-NEXT: mv a0, a2
24 ; RV32I-NEXT: .LBB0_6:
25 ; RV32I-NEXT: lw a2, 0(a1)
26 ; RV32I-NEXT: bgeu a0, a2, .LBB0_8
27 ; RV32I-NEXT: # %bb.7:
28 ; RV32I-NEXT: mv a0, a2
29 ; RV32I-NEXT: .LBB0_8:
30 ; RV32I-NEXT: lw a2, 0(a1)
31 ; RV32I-NEXT: bltu a0, a2, .LBB0_10
32 ; RV32I-NEXT: # %bb.9:
33 ; RV32I-NEXT: mv a0, a2
34 ; RV32I-NEXT: .LBB0_10:
35 ; RV32I-NEXT: lw a2, 0(a1)
36 ; RV32I-NEXT: bgeu a2, a0, .LBB0_12
37 ; RV32I-NEXT: # %bb.11:
38 ; RV32I-NEXT: mv a0, a2
39 ; RV32I-NEXT: .LBB0_12:
40 ; RV32I-NEXT: lw a2, 0(a1)
41 ; RV32I-NEXT: blt a2, a0, .LBB0_14
42 ; RV32I-NEXT: # %bb.13:
43 ; RV32I-NEXT: mv a0, a2
44 ; RV32I-NEXT: .LBB0_14:
45 ; RV32I-NEXT: lw a2, 0(a1)
46 ; RV32I-NEXT: bge a0, a2, .LBB0_16
47 ; RV32I-NEXT: # %bb.15:
48 ; RV32I-NEXT: mv a0, a2
49 ; RV32I-NEXT: .LBB0_16:
50 ; RV32I-NEXT: lw a2, 0(a1)
51 ; RV32I-NEXT: blt a0, a2, .LBB0_18
52 ; RV32I-NEXT: # %bb.17:
53 ; RV32I-NEXT: mv a0, a2
54 ; RV32I-NEXT: .LBB0_18:
55 ; RV32I-NEXT: lw a2, 0(a1)
56 ; RV32I-NEXT: bge a2, a0, .LBB0_20
57 ; RV32I-NEXT: # %bb.19:
58 ; RV32I-NEXT: mv a0, a2
59 ; RV32I-NEXT: .LBB0_20:
60 ; RV32I-NEXT: lw a2, 0(a1)
61 ; RV32I-NEXT: blez a2, .LBB0_22
62 ; RV32I-NEXT: # %bb.21:
63 ; RV32I-NEXT: mv a0, a2
64 ; RV32I-NEXT: .LBB0_22:
65 ; RV32I-NEXT: lw a3, 0(a1)
66 ; RV32I-NEXT: bgez a2, .LBB0_24
67 ; RV32I-NEXT: # %bb.23:
68 ; RV32I-NEXT: mv a0, a3
69 ; RV32I-NEXT: .LBB0_24:
70 ; RV32I-NEXT: lw a3, 0(a1)
71 ; RV32I-NEXT: li a4, 1024
72 ; RV32I-NEXT: blt a4, a3, .LBB0_26
73 ; RV32I-NEXT: # %bb.25:
74 ; RV32I-NEXT: mv a0, a3
75 ; RV32I-NEXT: .LBB0_26:
76 ; RV32I-NEXT: lw a1, 0(a1)
77 ; RV32I-NEXT: li a3, 2046
78 ; RV32I-NEXT: bltu a3, a2, .LBB0_28
79 ; RV32I-NEXT: # %bb.27:
80 ; RV32I-NEXT: mv a0, a1
81 ; RV32I-NEXT: .LBB0_28:
82 ; RV32I-NEXT: ret
83 ;
84 ; RV64I-LABEL: foo:
85 ; RV64I: # %bb.0:
86 ; RV64I-NEXT: lw a2, 0(a1)
87 ; RV64I-NEXT: beq a0, a2, .LBB0_2
88 ; RV64I-NEXT: # %bb.1:
89 ; RV64I-NEXT: mv a0, a2
90 ; RV64I-NEXT: .LBB0_2:
91 ; RV64I-NEXT: lw a2, 0(a1)
92 ; RV64I-NEXT: bne a0, a2, .LBB0_4
93 ; RV64I-NEXT: # %bb.3:
94 ; RV64I-NEXT: mv a0, a2
95 ; RV64I-NEXT: .LBB0_4:
96 ; RV64I-NEXT: lw a2, 0(a1)
97 ; RV64I-NEXT: bltu a2, a0, .LBB0_6
98 ; RV64I-NEXT: # %bb.5:
99 ; RV64I-NEXT: mv a0, a2
100 ; RV64I-NEXT: .LBB0_6:
101 ; RV64I-NEXT: lw a2, 0(a1)
102 ; RV64I-NEXT: bgeu a0, a2, .LBB0_8
103 ; RV64I-NEXT: # %bb.7:
104 ; RV64I-NEXT: mv a0, a2
105 ; RV64I-NEXT: .LBB0_8:
106 ; RV64I-NEXT: lw a2, 0(a1)
107 ; RV64I-NEXT: bltu a0, a2, .LBB0_10
108 ; RV64I-NEXT: # %bb.9:
109 ; RV64I-NEXT: mv a0, a2
110 ; RV64I-NEXT: .LBB0_10:
111 ; RV64I-NEXT: lw a2, 0(a1)
112 ; RV64I-NEXT: bgeu a2, a0, .LBB0_12
113 ; RV64I-NEXT: # %bb.11:
114 ; RV64I-NEXT: mv a0, a2
115 ; RV64I-NEXT: .LBB0_12:
116 ; RV64I-NEXT: lw a2, 0(a1)
117 ; RV64I-NEXT: blt a2, a0, .LBB0_14
118 ; RV64I-NEXT: # %bb.13:
119 ; RV64I-NEXT: mv a0, a2
120 ; RV64I-NEXT: .LBB0_14:
121 ; RV64I-NEXT: lw a2, 0(a1)
122 ; RV64I-NEXT: bge a0, a2, .LBB0_16
123 ; RV64I-NEXT: # %bb.15:
124 ; RV64I-NEXT: mv a0, a2
125 ; RV64I-NEXT: .LBB0_16:
126 ; RV64I-NEXT: lw a2, 0(a1)
127 ; RV64I-NEXT: blt a0, a2, .LBB0_18
128 ; RV64I-NEXT: # %bb.17:
129 ; RV64I-NEXT: mv a0, a2
130 ; RV64I-NEXT: .LBB0_18:
131 ; RV64I-NEXT: lw a2, 0(a1)
132 ; RV64I-NEXT: bge a2, a0, .LBB0_20
133 ; RV64I-NEXT: # %bb.19:
134 ; RV64I-NEXT: mv a0, a2
135 ; RV64I-NEXT: .LBB0_20:
136 ; RV64I-NEXT: lw a2, 0(a1)
137 ; RV64I-NEXT: blez a2, .LBB0_22
138 ; RV64I-NEXT: # %bb.21:
139 ; RV64I-NEXT: mv a0, a2
140 ; RV64I-NEXT: .LBB0_22:
141 ; RV64I-NEXT: lw a3, 0(a1)
142 ; RV64I-NEXT: bgez a2, .LBB0_24
143 ; RV64I-NEXT: # %bb.23:
144 ; RV64I-NEXT: mv a0, a3
145 ; RV64I-NEXT: .LBB0_24:
146 ; RV64I-NEXT: lw a3, 0(a1)
147 ; RV64I-NEXT: li a4, 1024
148 ; RV64I-NEXT: blt a4, a3, .LBB0_26
149 ; RV64I-NEXT: # %bb.25:
150 ; RV64I-NEXT: mv a0, a3
151 ; RV64I-NEXT: .LBB0_26:
152 ; RV64I-NEXT: lw a1, 0(a1)
153 ; RV64I-NEXT: li a3, 2046
154 ; RV64I-NEXT: bltu a3, a2, .LBB0_28
155 ; RV64I-NEXT: # %bb.27:
156 ; RV64I-NEXT: mv a0, a1
157 ; RV64I-NEXT: .LBB0_28:
158 ; RV64I-NEXT: ret
159 %val1 = load volatile i32, ptr %b
160 %tst1 = icmp eq i32 %a, %val1
161 %val2 = select i1 %tst1, i32 %a, i32 %val1
163 %val3 = load volatile i32, ptr %b
164 %tst2 = icmp ne i32 %val2, %val3
165 %val4 = select i1 %tst2, i32 %val2, i32 %val3
167 %val5 = load volatile i32, ptr %b
168 %tst3 = icmp ugt i32 %val4, %val5
169 %val6 = select i1 %tst3, i32 %val4, i32 %val5
171 %val7 = load volatile i32, ptr %b
172 %tst4 = icmp uge i32 %val6, %val7
173 %val8 = select i1 %tst4, i32 %val6, i32 %val7
175 %val9 = load volatile i32, ptr %b
176 %tst5 = icmp ult i32 %val8, %val9
177 %val10 = select i1 %tst5, i32 %val8, i32 %val9
179 %val11 = load volatile i32, ptr %b
180 %tst6 = icmp ule i32 %val10, %val11
181 %val12 = select i1 %tst6, i32 %val10, i32 %val11
183 %val13 = load volatile i32, ptr %b
184 %tst7 = icmp sgt i32 %val12, %val13
185 %val14 = select i1 %tst7, i32 %val12, i32 %val13
187 %val15 = load volatile i32, ptr %b
188 %tst8 = icmp sge i32 %val14, %val15
189 %val16 = select i1 %tst8, i32 %val14, i32 %val15
191 %val17 = load volatile i32, ptr %b
192 %tst9 = icmp slt i32 %val16, %val17
193 %val18 = select i1 %tst9, i32 %val16, i32 %val17
195 %val19 = load volatile i32, ptr %b
196 %tst10 = icmp sle i32 %val18, %val19
197 %val20 = select i1 %tst10, i32 %val18, i32 %val19
199 %val21 = load volatile i32, ptr %b
200 %tst11 = icmp slt i32 %val21, 1
201 %val22 = select i1 %tst11, i32 %val20, i32 %val21
203 %val23 = load volatile i32, ptr %b
204 %tst12 = icmp sgt i32 %val21, -1
205 %val24 = select i1 %tst12, i32 %val22, i32 %val23
207 %val25 = load volatile i32, ptr %b
208 %tst13 = icmp sgt i32 %val25, 1024
209 %val26 = select i1 %tst13, i32 %val24, i32 %val25
211 %val27 = load volatile i32, ptr %b
212 %tst14 = icmp ugt i32 %val21, 2046
213 %val28 = select i1 %tst14, i32 %val26, i32 %val27
214 ret i32 %val28
215 }
217 ; Test that we can ComputeNumSignBits across basic blocks when the live out is
218 ; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output.
219 define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind {
220 ; RV32I-LABEL: numsignbits:
221 ; RV32I: # %bb.0:
222 ; RV32I-NEXT: addi sp, sp, -16
223 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
224 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
225 ; RV32I-NEXT: mv s0, a3
226 ; RV32I-NEXT: beqz a0, .LBB1_2
227 ; RV32I-NEXT: # %bb.1:
228 ; RV32I-NEXT: mv s0, a2
229 ; RV32I-NEXT: .LBB1_2:
230 ; RV32I-NEXT: beqz a1, .LBB1_4
231 ; RV32I-NEXT: # %bb.3:
232 ; RV32I-NEXT: mv a0, s0
233 ; RV32I-NEXT: call bar
234 ; RV32I-NEXT: .LBB1_4:
235 ; RV32I-NEXT: mv a0, s0
236 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
237 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
238 ; RV32I-NEXT: addi sp, sp, 16
239 ; RV32I-NEXT: ret
240 ;
241 ; RV64I-LABEL: numsignbits:
242 ; RV64I: # %bb.0:
243 ; RV64I-NEXT: addi sp, sp, -16
244 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
245 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
246 ; RV64I-NEXT: mv s0, a3
247 ; RV64I-NEXT: beqz a0, .LBB1_2
248 ; RV64I-NEXT: # %bb.1:
249 ; RV64I-NEXT: mv s0, a2
250 ; RV64I-NEXT: .LBB1_2:
251 ; RV64I-NEXT: beqz a1, .LBB1_4
252 ; RV64I-NEXT: # %bb.3:
253 ; RV64I-NEXT: mv a0, s0
254 ; RV64I-NEXT: call bar
255 ; RV64I-NEXT: .LBB1_4:
256 ; RV64I-NEXT: mv a0, s0
257 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
258 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
259 ; RV64I-NEXT: addi sp, sp, 16
260 ; RV64I-NEXT: ret
261 %5 = icmp eq i16 %0, 0
262 %6 = select i1 %5, i16 %3, i16 %2
263 %7 = icmp eq i16 %1, 0
264 br i1 %7, label %9, label %8
266 8: ; preds = %4
267 tail call void @bar(i16 signext %6)
268 br label %9
270 9: ; preds = %8, %4
271 ret i16 %6
272 }
274 declare void @bar(i16 signext)
276 define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) {
277 ; RV32I-LABEL: select_sge_int16min:
278 ; RV32I: # %bb.0:
279 ; RV32I-NEXT: lui a3, 1048560
280 ; RV32I-NEXT: addi a3, a3, -1
281 ; RV32I-NEXT: blt a3, a0, .LBB2_2
282 ; RV32I-NEXT: # %bb.1:
283 ; RV32I-NEXT: mv a1, a2
284 ; RV32I-NEXT: .LBB2_2:
285 ; RV32I-NEXT: mv a0, a1
286 ; RV32I-NEXT: ret
287 ;
288 ; RV64I-LABEL: select_sge_int16min:
289 ; RV64I: # %bb.0:
290 ; RV64I-NEXT: lui a3, 1048560
291 ; RV64I-NEXT: addiw a3, a3, -1
292 ; RV64I-NEXT: blt a3, a0, .LBB2_2
293 ; RV64I-NEXT: # %bb.1:
294 ; RV64I-NEXT: mv a1, a2
295 ; RV64I-NEXT: .LBB2_2:
296 ; RV64I-NEXT: mv a0, a1
297 ; RV64I-NEXT: ret
298 %a = icmp sge i32 %x, -65536
299 %b = select i1 %a, i32 %y, i32 %z
300 ret i32 %b
301 }
303 define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
304 ; RV32I-LABEL: select_sge_int32min:
305 ; RV32I: # %bb.0:
306 ; RV32I-NEXT: li a6, -1
307 ; RV32I-NEXT: bne a1, a6, .LBB3_2
308 ; RV32I-NEXT: # %bb.1:
309 ; RV32I-NEXT: slti a0, a0, 0
310 ; RV32I-NEXT: j .LBB3_3
311 ; RV32I-NEXT: .LBB3_2:
312 ; RV32I-NEXT: slti a0, a1, 0
313 ; RV32I-NEXT: xori a0, a0, 1
314 ; RV32I-NEXT: .LBB3_3:
315 ; RV32I-NEXT: bnez a0, .LBB3_5
316 ; RV32I-NEXT: # %bb.4:
317 ; RV32I-NEXT: mv a2, a4
318 ; RV32I-NEXT: mv a3, a5
319 ; RV32I-NEXT: .LBB3_5:
320 ; RV32I-NEXT: mv a0, a2
321 ; RV32I-NEXT: mv a1, a3
322 ; RV32I-NEXT: ret
323 ;
324 ; RV64I-LABEL: select_sge_int32min:
325 ; RV64I: # %bb.0:
326 ; RV64I-NEXT: lui a3, 524288
327 ; RV64I-NEXT: addi a3, a3, -1
328 ; RV64I-NEXT: blt a3, a0, .LBB3_2
329 ; RV64I-NEXT: # %bb.1:
330 ; RV64I-NEXT: mv a1, a2
331 ; RV64I-NEXT: .LBB3_2:
332 ; RV64I-NEXT: mv a0, a1
333 ; RV64I-NEXT: ret
334 %a = icmp sge i64 %x, -2147483648
335 %b = select i1 %a, i64 %y, i64 %z
336 ret i64 %b
337 }