1 ; Test 128-bit addition in which the second operand is variable.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
8 ; Test register addition.
9 define void @f1(ptr %ptr) {
14 %value = load i128, ptr %ptr
15 %add = add i128 %value, %value
16 store i128 %add, ptr %ptr
20 ; Test memory addition with no offset. Making the load of %a volatile
21 ; should force the memory operand to be %b.
22 define void @f2(ptr %aptr, i64 %addr) {
24 ; CHECK: alg {{%r[0-5]}}, 8(%r3)
25 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
27 %bptr = inttoptr i64 %addr to ptr
28 %a = load volatile i128, ptr %aptr
29 %b = load i128, ptr %bptr
30 %add = add i128 %a, %b
31 store i128 %add, ptr %aptr
35 ; Test the highest aligned offset that is in range of both ALG and ALCG.
36 define void @f3(ptr %aptr, i64 %base) {
38 ; CHECK: alg {{%r[0-5]}}, 524280(%r3)
39 ; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
41 %addr = add i64 %base, 524272
42 %bptr = inttoptr i64 %addr to ptr
43 %a = load volatile i128, ptr %aptr
44 %b = load i128, ptr %bptr
45 %add = add i128 %a, %b
46 store i128 %add, ptr %aptr
50 ; Test the next doubleword up, which requires separate address logic for ALG.
51 define void @f4(ptr %aptr, i64 %base) {
53 ; CHECK: lay [[BASE:%r[1-5]]], 524280(%r3)
54 ; CHECK: alg {{%r[0-5]}}, 8([[BASE]])
55 ; CHECK: alcg {{%r[0-5]}}, 524280(%r3)
57 %addr = add i64 %base, 524280
58 %bptr = inttoptr i64 %addr to ptr
59 %a = load volatile i128, ptr %aptr
60 %b = load i128, ptr %bptr
61 %add = add i128 %a, %b
62 store i128 %add, ptr %aptr
66 ; Test the next doubleword after that, which requires separate logic for
68 define void @f5(ptr %aptr, i64 %base) {
70 ; CHECK: alg {{%r[0-5]}}, 8({{%r[1-5]}})
71 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
73 %addr = add i64 %base, 524288
74 %bptr = inttoptr i64 %addr to ptr
75 %a = load volatile i128, ptr %aptr
76 %b = load i128, ptr %bptr
77 %add = add i128 %a, %b
78 store i128 %add, ptr %aptr
82 ; Test the lowest displacement that is in range of both ALG and ALCG.
83 define void @f6(ptr %aptr, i64 %base) {
85 ; CHECK: alg {{%r[0-5]}}, -524280(%r3)
86 ; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
88 %addr = add i64 %base, -524288
89 %bptr = inttoptr i64 %addr to ptr
90 %a = load volatile i128, ptr %aptr
91 %b = load i128, ptr %bptr
92 %add = add i128 %a, %b
93 store i128 %add, ptr %aptr
97 ; Test the next doubleword down, which is out of range of the ALCG.
98 define void @f7(ptr %aptr, i64 %base) {
100 ; CHECK: alg {{%r[0-5]}}, -524288(%r3)
101 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
103 %addr = add i64 %base, -524296
104 %bptr = inttoptr i64 %addr to ptr
105 %a = load volatile i128, ptr %aptr
106 %b = load i128, ptr %bptr
107 %add = add i128 %a, %b
108 store i128 %add, ptr %aptr
112 ; Check that additions of spilled values can use ALG and ALCG rather than
114 define void @f8(ptr %ptr0) {
116 ; CHECK: brasl %r14, foo@PLT
117 ; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
118 ; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
120 %ptr1 = getelementptr i128, ptr %ptr0, i128 2
121 %ptr2 = getelementptr i128, ptr %ptr0, i128 4
122 %ptr3 = getelementptr i128, ptr %ptr0, i128 6
123 %ptr4 = getelementptr i128, ptr %ptr0, i128 8
124 %ptr5 = getelementptr i128, ptr %ptr0, i128 10
126 %val0 = load i128, ptr %ptr0
127 %val1 = load i128, ptr %ptr1
128 %val2 = load i128, ptr %ptr2
129 %val3 = load i128, ptr %ptr3
130 %val4 = load i128, ptr %ptr4
131 %val5 = load i128, ptr %ptr5
133 %retptr = call ptr@foo()
135 %ret = load i128, ptr %retptr
136 %add0 = add i128 %ret, %val0
137 %add1 = add i128 %add0, %val1
138 %add2 = add i128 %add1, %val2
139 %add3 = add i128 %add2, %val3
140 %add4 = add i128 %add3, %val4
141 %add5 = add i128 %add4, %val5
142 store i128 %add5, ptr %retptr