| blob | 5219c74e35817c3c791d9f83b4bb1768385c70ad |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=thumbv8.1m.main-none-eabi | FileCheck %s
4 define i32 @ori32i32_eq(i32 %x, i32 %y) {
5 ; CHECK-LABEL: ori32i32_eq:
6 ; CHECK: @ %bb.0:
7 ; CHECK-NEXT: and r0, r0, #1
8 ; CHECK-NEXT: cmp r1, #0
9 ; CHECK-NEXT: csinc r0, r0, zr, ne
10 ; CHECK-NEXT: bx lr
11 %xa = and i32 %x, 1
12 %c = icmp eq i32 %y, 0
13 %cz = zext i1 %c to i32
14 %a = or i32 %xa, %cz
15 ret i32 %a
16 }
18 define i32 @ori32_eq_c(i32 %x, i32 %y) {
19 ; CHECK-LABEL: ori32_eq_c:
20 ; CHECK: @ %bb.0:
21 ; CHECK-NEXT: and r0, r0, #1
22 ; CHECK-NEXT: cmp r1, #0
23 ; CHECK-NEXT: csinc r0, r0, zr, ne
24 ; CHECK-NEXT: bx lr
25 %xa = and i32 %x, 1
26 %c = icmp eq i32 %y, 0
27 %cz = zext i1 %c to i32
28 %a = or i32 %cz, %xa
29 ret i32 %a
30 }
32 define i32 @ori32i64_eq(i32 %x, i64 %y) {
33 ; CHECK-LABEL: ori32i64_eq:
34 ; CHECK: @ %bb.0:
35 ; CHECK-NEXT: orrs.w r1, r2, r3
36 ; CHECK-NEXT: and r0, r0, #1
37 ; CHECK-NEXT: csinc r0, r0, zr, ne
38 ; CHECK-NEXT: bx lr
39 %xa = and i32 %x, 1
40 %c = icmp eq i64 %y, 0
41 %cz = zext i1 %c to i32
42 %a = or i32 %xa, %cz
43 ret i32 %a
44 }
46 define i32 @ori32_sgt(i32 %x, i32 %y) {
47 ; CHECK-LABEL: ori32_sgt:
48 ; CHECK: @ %bb.0:
49 ; CHECK-NEXT: and r0, r0, #1
50 ; CHECK-NEXT: cmp r1, #0
51 ; CHECK-NEXT: csinc r0, r0, zr, le
52 ; CHECK-NEXT: bx lr
53 %xa = and i32 %x, 1
54 %c = icmp sgt i32 %y, 0
55 %cz = zext i1 %c to i32
56 %a = or i32 %xa, %cz
57 ret i32 %a
58 }
60 ; Negative test - too many demanded bits
61 define i32 @ori32_toomanybits(i32 %x, i32 %y) {
62 ; CHECK-LABEL: ori32_toomanybits:
63 ; CHECK: @ %bb.0:
64 ; CHECK-NEXT: and r0, r0, #3
65 ; CHECK-NEXT: cmp r1, #0
66 ; CHECK-NEXT: it eq
67 ; CHECK-NEXT: orreq r0, r0, #1
68 ; CHECK-NEXT: bx lr
69 %xa = and i32 %x, 3
70 %c = icmp eq i32 %y, 0
71 %cz = zext i1 %c to i32
72 %a = or i32 %xa, %cz
73 ret i32 %a
74 }
76 define i32 @andi32_ne(i8 %x, i8 %y) {
77 ; CHECK-LABEL: andi32_ne:
78 ; CHECK: @ %bb.0:
79 ; CHECK-NEXT: tst.w r0, #255
80 ; CHECK-NEXT: cset r0, eq
81 ; CHECK-NEXT: tst.w r1, #255
82 ; CHECK-NEXT: csel r0, zr, r0, eq
83 ; CHECK-NEXT: bx lr
84 %xc = icmp eq i8 %x, 0
85 %xa = zext i1 %xc to i32
86 %c = icmp ne i8 %y, 0
87 %cz = zext i1 %c to i32
88 %a = and i32 %xa, %cz
89 ret i32 %a
90 }
92 define i32 @andi32_sgt(i8 %x, i8 %y) {
93 ; CHECK-LABEL: andi32_sgt:
94 ; CHECK: @ %bb.0:
95 ; CHECK-NEXT: tst.w r0, #255
96 ; CHECK-NEXT: sxtb r1, r1
97 ; CHECK-NEXT: cset r0, eq
98 ; CHECK-NEXT: cmp r1, #0
99 ; CHECK-NEXT: csel r0, zr, r0, le
100 ; CHECK-NEXT: bx lr
101 %xc = icmp eq i8 %x, 0
102 %xa = zext i1 %xc to i32
103 %c = icmp sgt i8 %y, 0
104 %cz = zext i1 %c to i32
105 %a = and i32 %xa, %cz
106 ret i32 %a
107 }
109 define i64 @ori64i32_eq(i64 %x, i32 %y) {
110 ; CHECK-LABEL: ori64i32_eq:
111 ; CHECK: @ %bb.0:
112 ; CHECK-NEXT: cmp r2, #0
113 ; CHECK-NEXT: and r0, r0, #1
114 ; CHECK-NEXT: cset r1, eq
115 ; CHECK-NEXT: orrs r0, r1
116 ; CHECK-NEXT: movs r1, #0
117 ; CHECK-NEXT: bx lr
118 %xa = and i64 %x, 1
119 %c = icmp eq i32 %y, 0
120 %cz = zext i1 %c to i64
121 %a = or i64 %xa, %cz
122 ret i64 %a
123 }
125 define i64 @ori64i64_eq(i64 %x, i64 %y) {
126 ; CHECK-LABEL: ori64i64_eq:
127 ; CHECK: @ %bb.0:
128 ; CHECK-NEXT: orrs.w r1, r2, r3
129 ; CHECK-NEXT: and r0, r0, #1
130 ; CHECK-NEXT: cset r1, eq
131 ; CHECK-NEXT: orrs r0, r1
132 ; CHECK-NEXT: movs r1, #0
133 ; CHECK-NEXT: bx lr
134 %xa = and i64 %x, 1
135 %c = icmp eq i64 %y, 0
136 %cz = zext i1 %c to i64
137 %a = or i64 %xa, %cz
138 ret i64 %a
139 }
141 define i64 @ori64_eq_c(i64 %x, i32 %y) {
142 ; CHECK-LABEL: ori64_eq_c:
143 ; CHECK: @ %bb.0:
144 ; CHECK-NEXT: cmp r2, #0
145 ; CHECK-NEXT: and r0, r0, #1
146 ; CHECK-NEXT: cset r1, eq
147 ; CHECK-NEXT: orrs r0, r1
148 ; CHECK-NEXT: movs r1, #0
149 ; CHECK-NEXT: bx lr
150 %xa = and i64 %x, 1
151 %c = icmp eq i32 %y, 0
152 %cz = zext i1 %c to i64
153 %a = or i64 %cz, %xa
154 ret i64 %a
155 }
157 define i64 @andi64_ne(i8 %x, i8 %y) {
158 ; CHECK-LABEL: andi64_ne:
159 ; CHECK: @ %bb.0:
160 ; CHECK-NEXT: tst.w r0, #255
161 ; CHECK-NEXT: cset r0, eq
162 ; CHECK-NEXT: tst.w r1, #255
163 ; CHECK-NEXT: csel r0, zr, r0, eq
164 ; CHECK-NEXT: movs r1, #0
165 ; CHECK-NEXT: bx lr
166 %xc = icmp eq i8 %x, 0
167 %xa = zext i1 %xc to i64
168 %c = icmp ne i8 %y, 0
169 %cz = zext i1 %c to i64
170 %a = and i64 %xa, %cz
171 ret i64 %a
172 }
174 ; Check for multiple uses on the csinc
175 define i32 @t5(i32 %f.0, i32 %call) {
176 ; CHECK-LABEL: t5:
177 ; CHECK: @ %bb.0: @ %entry
178 ; CHECK-NEXT: cmp r1, #0
179 ; CHECK-NEXT: cset r1, ne
180 ; CHECK-NEXT: cmp r0, #13
181 ; CHECK-NEXT: cset r0, eq
182 ; CHECK-NEXT: and.w r2, r0, r1
183 ; CHECK-NEXT: orrs r0, r1
184 ; CHECK-NEXT: eor r0, r0, #1
185 ; CHECK-NEXT: orrs r0, r2
186 ; CHECK-NEXT: bx lr
187 entry:
188 %tobool1.i = icmp ne i32 %call, 0
189 %cmp = icmp eq i32 %f.0, 13
190 %or.cond = select i1 %cmp, i1 %tobool1.i, i1 false
191 %or.cond7.not = select i1 %cmp, i1 true, i1 %tobool1.i
192 %or.cond7.not.not = xor i1 %or.cond7.not, true
193 %not.or.cond12 = select i1 %or.cond, i1 true, i1 %or.cond7.not.not
194 %g.0 = zext i1 %not.or.cond12 to i32
195 ret i32 %g.0
196 }
198 define i32 @test(i32 %a, i32 %b) {
199 ; CHECK-LABEL: test:
200 ; CHECK: @ %bb.0: @ %entry
201 ; CHECK-NEXT: movs r2, #1
202 ; CHECK-NEXT: cmp r1, r0
203 ; CHECK-NEXT: lsr.w r2, r2, r1
204 ; CHECK-NEXT: csinc r0, r2, zr, le
205 ; CHECK-NEXT: bx lr
206 entry:
207 %cmp = icmp sgt i32 %b, %a
208 %b.op = lshr i32 1, %b
209 %shr = select i1 %cmp, i32 1, i32 %b.op
210 ret i32 %shr
211 }