1 ; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -show-mc-encoding | FileCheck %s
2 define void @coproc(ptr %i) nounwind {
4 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
5 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
6 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
7 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
8 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
9 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
10 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
11 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
12 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
13 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
14 ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
15 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
16 ; CHECK: cdp p7, #3, c1, c1, c1, #5
17 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
18 ; CHECK: cdp2 p7, #3, c1, c1, c1, #5
19 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
20 ; CHECK: ldc p7, c3, [r{{[0-9]+}}]
21 tail call void @llvm.arm.ldc(i32 7, i32 3, ptr %i) nounwind
22 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
23 tail call void @llvm.arm.ldcl(i32 7, i32 3, ptr %i) nounwind
24 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
25 tail call void @llvm.arm.ldc2(i32 7, i32 3, ptr %i) nounwind
26 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
27 tail call void @llvm.arm.ldc2l(i32 7, i32 3, ptr %i) nounwind
28 ; CHECK: stc p7, c3, [r{{[0-9]+}}]
29 tail call void @llvm.arm.stc(i32 7, i32 3, ptr %i) nounwind
30 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
31 tail call void @llvm.arm.stcl(i32 7, i32 3, ptr %i) nounwind
32 ; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
33 tail call void @llvm.arm.stc2(i32 7, i32 3, ptr %i) nounwind
34 ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
35 tail call void @llvm.arm.stc2l(i32 7, i32 3, ptr %i) nounwind
36 ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
37 %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
38 ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
39 %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
43 define hidden void @cond_cdp(i32 %a) {
44 ; CHECK-LABEL: cond_cdp:
46 %tobool = icmp eq i32 %a, 0
47 br i1 %tobool, label %if.end, label %if.then
51 ; CHECK: cdpne p15, #0, c0, c0, c0, #0 @ encoding: [0x00,0xee,0x00,0x0f]
52 tail call void @llvm.arm.cdp(i32 15, i32 0, i32 0, i32 0, i32 0, i32 0)
59 declare void @llvm.arm.ldc(i32, i32, ptr) nounwind
61 declare void @llvm.arm.ldcl(i32, i32, ptr) nounwind
63 declare void @llvm.arm.ldc2(i32, i32, ptr) nounwind
65 declare void @llvm.arm.ldc2l(i32, i32, ptr) nounwind
67 declare void @llvm.arm.stc(i32, i32, ptr) nounwind
69 declare void @llvm.arm.stcl(i32, i32, ptr) nounwind
71 declare void @llvm.arm.stc2(i32, i32, ptr) nounwind
73 declare void @llvm.arm.stc2l(i32, i32, ptr) nounwind
75 declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
77 declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
79 declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
81 declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
83 declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
85 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
87 declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
89 declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
91 declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
93 declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind