| blob | 4ed00a9d66bd35ded5c6aaec40015c47aca68192 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
6 ; fold (srem x, 1) -> 0
7 define i32 @combine_srem_by_one(i32 %x) {
8 ; CHECK-LABEL: combine_srem_by_one:
9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: xorl %eax, %eax
11 ; CHECK-NEXT: retq
12 %1 = srem i32 %x, 1
13 ret i32 %1
14 }
16 define <4 x i32> @combine_vec_srem_by_one(<4 x i32> %x) {
17 ; SSE-LABEL: combine_vec_srem_by_one:
18 ; SSE: # %bb.0:
19 ; SSE-NEXT: xorps %xmm0, %xmm0
20 ; SSE-NEXT: retq
21 ;
22 ; AVX-LABEL: combine_vec_srem_by_one:
23 ; AVX: # %bb.0:
24 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
25 ; AVX-NEXT: retq
26 %1 = srem <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
27 ret <4 x i32> %1
28 }
30 ; fold (srem x, -1) -> 0
31 define i32 @combine_srem_by_negone(i32 %x) {
32 ; CHECK-LABEL: combine_srem_by_negone:
33 ; CHECK: # %bb.0:
34 ; CHECK-NEXT: xorl %eax, %eax
35 ; CHECK-NEXT: retq
36 %1 = srem i32 %x, -1
37 ret i32 %1
38 }
40 define <4 x i32> @combine_vec_srem_by_negone(<4 x i32> %x) {
41 ; SSE-LABEL: combine_vec_srem_by_negone:
42 ; SSE: # %bb.0:
43 ; SSE-NEXT: xorps %xmm0, %xmm0
44 ; SSE-NEXT: retq
45 ;
46 ; AVX-LABEL: combine_vec_srem_by_negone:
47 ; AVX: # %bb.0:
48 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
49 ; AVX-NEXT: retq
50 %1 = srem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
51 ret <4 x i32> %1
52 }
54 ; TODO fold (srem x, INT_MIN)
55 define i32 @combine_srem_by_minsigned(i32 %x) {
56 ; CHECK-LABEL: combine_srem_by_minsigned:
57 ; CHECK: # %bb.0:
58 ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
59 ; CHECK-NEXT: leal 2147483647(%rdi), %eax
60 ; CHECK-NEXT: testl %edi, %edi
61 ; CHECK-NEXT: cmovnsl %edi, %eax
62 ; CHECK-NEXT: andl $-2147483648, %eax # imm = 0x80000000
63 ; CHECK-NEXT: addl %edi, %eax
64 ; CHECK-NEXT: retq
65 %1 = srem i32 %x, -2147483648
66 ret i32 %1
67 }
69 define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
70 ; SSE-LABEL: combine_vec_srem_by_minsigned:
71 ; SSE: # %bb.0:
72 ; SSE-NEXT: movdqa %xmm0, %xmm1
73 ; SSE-NEXT: psrad $31, %xmm1
74 ; SSE-NEXT: psrld $1, %xmm1
75 ; SSE-NEXT: paddd %xmm0, %xmm1
76 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
77 ; SSE-NEXT: paddd %xmm1, %xmm0
78 ; SSE-NEXT: retq
79 ;
80 ; AVX1-LABEL: combine_vec_srem_by_minsigned:
81 ; AVX1: # %bb.0:
82 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
83 ; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
84 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
85 ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
86 ; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0
87 ; AVX1-NEXT: retq
88 ;
89 ; AVX2-LABEL: combine_vec_srem_by_minsigned:
90 ; AVX2: # %bb.0:
91 ; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
92 ; AVX2-NEXT: vpsrld $1, %xmm1, %xmm1
93 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
94 ; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
95 ; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
96 ; AVX2-NEXT: vpaddd %xmm0, %xmm1, %xmm0
97 ; AVX2-NEXT: retq
98 %1 = srem <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
99 ret <4 x i32> %1
100 }
102 ; fold (srem 0, x) -> 0
103 define i32 @combine_srem_zero(i32 %x) {
104 ; CHECK-LABEL: combine_srem_zero:
105 ; CHECK: # %bb.0:
106 ; CHECK-NEXT: xorl %eax, %eax
107 ; CHECK-NEXT: retq
108 %1 = srem i32 0, %x
109 ret i32 %1
110 }
112 define <4 x i32> @combine_vec_srem_zero(<4 x i32> %x) {
113 ; SSE-LABEL: combine_vec_srem_zero:
114 ; SSE: # %bb.0:
115 ; SSE-NEXT: xorps %xmm0, %xmm0
116 ; SSE-NEXT: retq
117 ;
118 ; AVX-LABEL: combine_vec_srem_zero:
119 ; AVX: # %bb.0:
120 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
121 ; AVX-NEXT: retq
122 %1 = srem <4 x i32> zeroinitializer, %x
123 ret <4 x i32> %1
124 }
126 ; fold (srem x, x) -> 0
127 define i32 @combine_srem_dupe(i32 %x) {
128 ; CHECK-LABEL: combine_srem_dupe:
129 ; CHECK: # %bb.0:
130 ; CHECK-NEXT: xorl %eax, %eax
131 ; CHECK-NEXT: retq
132 %1 = srem i32 %x, %x
133 ret i32 %1
134 }
136 define <4 x i32> @combine_vec_srem_dupe(<4 x i32> %x) {
137 ; SSE-LABEL: combine_vec_srem_dupe:
138 ; SSE: # %bb.0:
139 ; SSE-NEXT: xorps %xmm0, %xmm0
140 ; SSE-NEXT: retq
141 ;
142 ; AVX-LABEL: combine_vec_srem_dupe:
143 ; AVX: # %bb.0:
144 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
145 ; AVX-NEXT: retq
146 %1 = srem <4 x i32> %x, %x
147 ret <4 x i32> %1
148 }
150 ; fold (srem x, y) -> (urem x, y) iff x and y are positive
151 define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
152 ; SSE-LABEL: combine_vec_srem_by_pos0:
153 ; SSE: # %bb.0:
154 ; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
155 ; SSE-NEXT: retq
156 ;
157 ; AVX1-LABEL: combine_vec_srem_by_pos0:
158 ; AVX1: # %bb.0:
159 ; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
160 ; AVX1-NEXT: retq
161 ;
162 ; AVX2-LABEL: combine_vec_srem_by_pos0:
163 ; AVX2: # %bb.0:
164 ; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [3,3,3,3]
165 ; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
166 ; AVX2-NEXT: retq
167 %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
168 %2 = srem <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
169 ret <4 x i32> %2
170 }
172 define <4 x i32> @combine_vec_srem_by_pos1(<4 x i32> %x) {
173 ; SSE-LABEL: combine_vec_srem_by_pos1:
174 ; SSE: # %bb.0:
175 ; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
176 ; SSE-NEXT: retq
177 ;
178 ; AVX-LABEL: combine_vec_srem_by_pos1:
179 ; AVX: # %bb.0:
180 ; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
181 ; AVX-NEXT: retq
182 %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
183 %2 = srem <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
184 ret <4 x i32> %2
185 }
187 ; fold (srem x, (1 << c)) -> x - (x / (1 << c)) * (1 << c).
188 define <4 x i32> @combine_vec_srem_by_pow2a(<4 x i32> %x) {
189 ; SSE-LABEL: combine_vec_srem_by_pow2a:
190 ; SSE: # %bb.0:
191 ; SSE-NEXT: movdqa %xmm0, %xmm1
192 ; SSE-NEXT: psrad $31, %xmm1
193 ; SSE-NEXT: psrld $30, %xmm1
194 ; SSE-NEXT: paddd %xmm0, %xmm1
195 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
196 ; SSE-NEXT: psubd %xmm1, %xmm0
197 ; SSE-NEXT: retq
198 ;
199 ; AVX1-LABEL: combine_vec_srem_by_pow2a:
200 ; AVX1: # %bb.0:
201 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
202 ; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
203 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
204 ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
205 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
206 ; AVX1-NEXT: retq
207 ;
208 ; AVX2-LABEL: combine_vec_srem_by_pow2a:
209 ; AVX2: # %bb.0:
210 ; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
211 ; AVX2-NEXT: vpsrld $30, %xmm1, %xmm1
212 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
213 ; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967292,4294967292,4294967292,4294967292]
214 ; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
215 ; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
216 ; AVX2-NEXT: retq
217 %1 = srem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
218 ret <4 x i32> %1
219 }
221 define <4 x i32> @combine_vec_srem_by_pow2a_neg(<4 x i32> %x) {
222 ; SSE-LABEL: combine_vec_srem_by_pow2a_neg:
223 ; SSE: # %bb.0:
224 ; SSE-NEXT: movdqa %xmm0, %xmm1
225 ; SSE-NEXT: psrad $31, %xmm1
226 ; SSE-NEXT: psrld $30, %xmm1
227 ; SSE-NEXT: paddd %xmm0, %xmm1
228 ; SSE-NEXT: psrld $2, %xmm1
229 ; SSE-NEXT: pxor %xmm2, %xmm2
230 ; SSE-NEXT: psubd %xmm1, %xmm2
231 ; SSE-NEXT: pslld $2, %xmm2
232 ; SSE-NEXT: paddd %xmm2, %xmm0
233 ; SSE-NEXT: retq
234 ;
235 ; AVX-LABEL: combine_vec_srem_by_pow2a_neg:
236 ; AVX: # %bb.0:
237 ; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
238 ; AVX-NEXT: vpsrld $30, %xmm1, %xmm1
239 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm1
240 ; AVX-NEXT: vpsrld $2, %xmm1, %xmm1
241 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
242 ; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
243 ; AVX-NEXT: vpslld $2, %xmm1, %xmm1
244 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: retq
246 %1 = srem <4 x i32> %x, <i32 -4, i32 -4, i32 -4, i32 -4>
247 ret <4 x i32> %1
248 }
250 define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
251 ; SSE-LABEL: combine_vec_srem_by_pow2b:
252 ; SSE: # %bb.0:
253 ; SSE-NEXT: movdqa %xmm0, %xmm1
254 ; SSE-NEXT: psrad $31, %xmm1
255 ; SSE-NEXT: movdqa %xmm1, %xmm2
256 ; SSE-NEXT: psrld $29, %xmm2
257 ; SSE-NEXT: movdqa %xmm1, %xmm3
258 ; SSE-NEXT: psrld $31, %xmm3
259 ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
260 ; SSE-NEXT: psrld $30, %xmm1
261 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
262 ; SSE-NEXT: paddd %xmm0, %xmm1
263 ; SSE-NEXT: movdqa %xmm1, %xmm2
264 ; SSE-NEXT: psrad $3, %xmm2
265 ; SSE-NEXT: movdqa %xmm1, %xmm3
266 ; SSE-NEXT: psrad $1, %xmm3
267 ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
268 ; SSE-NEXT: psrad $2, %xmm1
269 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
270 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
271 ; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
272 ; SSE-NEXT: psubd %xmm1, %xmm0
273 ; SSE-NEXT: retq
274 ;
275 ; AVX1-LABEL: combine_vec_srem_by_pow2b:
276 ; AVX1: # %bb.0:
277 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
278 ; AVX1-NEXT: vpsrld $29, %xmm1, %xmm2
279 ; AVX1-NEXT: vpsrld $31, %xmm1, %xmm3
280 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
281 ; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
282 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
283 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
284 ; AVX1-NEXT: vpsrad $3, %xmm1, %xmm2
285 ; AVX1-NEXT: vpsrad $1, %xmm1, %xmm3
286 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
287 ; AVX1-NEXT: vpsrad $2, %xmm1, %xmm1
288 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
289 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
290 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
291 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
292 ; AVX1-NEXT: retq
293 ;
294 ; AVX2-LABEL: combine_vec_srem_by_pow2b:
295 ; AVX2: # %bb.0:
296 ; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
297 ; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
298 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
299 ; AVX2-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,1,2,3]
300 ; AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
301 ; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
302 ; AVX2-NEXT: vpsllvd %xmm2, %xmm1, %xmm1
303 ; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
304 ; AVX2-NEXT: retq
305 %1 = srem <4 x i32> %x, <i32 1, i32 2, i32 4, i32 8>
306 ret <4 x i32> %1
307 }
309 define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
310 ; SSE-LABEL: combine_vec_srem_by_pow2b_neg:
311 ; SSE: # %bb.0:
312 ; SSE-NEXT: movdqa %xmm0, %xmm1
313 ; SSE-NEXT: psrad $31, %xmm1
314 ; SSE-NEXT: movdqa %xmm1, %xmm2
315 ; SSE-NEXT: psrld $28, %xmm2
316 ; SSE-NEXT: movdqa %xmm1, %xmm3
317 ; SSE-NEXT: psrld $30, %xmm3
318 ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
319 ; SSE-NEXT: movdqa %xmm1, %xmm2
320 ; SSE-NEXT: psrld $29, %xmm2
321 ; SSE-NEXT: psrld $31, %xmm1
322 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
323 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
324 ; SSE-NEXT: paddd %xmm0, %xmm1
325 ; SSE-NEXT: movdqa %xmm1, %xmm2
326 ; SSE-NEXT: psrad $4, %xmm2
327 ; SSE-NEXT: movdqa %xmm1, %xmm3
328 ; SSE-NEXT: psrad $2, %xmm3
329 ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
330 ; SSE-NEXT: movdqa %xmm1, %xmm2
331 ; SSE-NEXT: psrad $3, %xmm2
332 ; SSE-NEXT: psrld $1, %xmm1
333 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
334 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
335 ; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
336 ; SSE-NEXT: paddd %xmm1, %xmm0
337 ; SSE-NEXT: retq
338 ;
339 ; AVX1-LABEL: combine_vec_srem_by_pow2b_neg:
340 ; AVX1: # %bb.0:
341 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
342 ; AVX1-NEXT: vpsrld $28, %xmm1, %xmm2
343 ; AVX1-NEXT: vpsrld $30, %xmm1, %xmm3
344 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
345 ; AVX1-NEXT: vpsrld $29, %xmm1, %xmm3
346 ; AVX1-NEXT: vpsrld $31, %xmm1, %xmm1
347 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
348 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
349 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
350 ; AVX1-NEXT: vpsrad $4, %xmm1, %xmm2
351 ; AVX1-NEXT: vpsrad $2, %xmm1, %xmm3
352 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
353 ; AVX1-NEXT: vpsrad $3, %xmm1, %xmm3
354 ; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
355 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
356 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
357 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
358 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
359 ; AVX1-NEXT: retq
360 ;
361 ; AVX2-LABEL: combine_vec_srem_by_pow2b_neg:
362 ; AVX2: # %bb.0:
363 ; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
364 ; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
365 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
366 ; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
367 ; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
368 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
369 ; AVX2-NEXT: retq
370 %1 = srem <4 x i32> %x, <i32 -2, i32 -4, i32 -8, i32 -16>
371 ret <4 x i32> %1
372 }
374 ; FIXME: PR55271 - srem(undef, 3) != undef
375 ; Use PSLLI intrinsic to postpone the undef creation until after urem-by-constant expansion
376 define <4 x i32> @combine_vec_srem_undef_by_3(<4 x i32> %in) {
377 ; CHECK-LABEL: combine_vec_srem_undef_by_3:
378 ; CHECK: # %bb.0:
379 ; CHECK-NEXT: retq
380 %x = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 0)
381 %y = srem <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
382 ret <4 x i32> %y
383 }
384 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
386 ; OSS-Fuzz #6883
387 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883
388 define i32 @ossfuzz6883() {
389 ; CHECK-LABEL: ossfuzz6883:
390 ; CHECK: # %bb.0:
391 ; CHECK-NEXT: movl (%rax), %ecx
392 ; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
393 ; CHECK-NEXT: xorl %edx, %edx
394 ; CHECK-NEXT: idivl %ecx
395 ; CHECK-NEXT: movl %eax, %esi
396 ; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
397 ; CHECK-NEXT: xorl %edx, %edx
398 ; CHECK-NEXT: divl %ecx
399 ; CHECK-NEXT: movl %eax, %edi
400 ; CHECK-NEXT: movl %esi, %eax
401 ; CHECK-NEXT: cltd
402 ; CHECK-NEXT: idivl %edi
403 ; CHECK-NEXT: movl %edx, %esi
404 ; CHECK-NEXT: movl %ecx, %eax
405 ; CHECK-NEXT: cltd
406 ; CHECK-NEXT: idivl %esi
407 ; CHECK-NEXT: movl %edx, %edi
408 ; CHECK-NEXT: movl %ecx, %eax
409 ; CHECK-NEXT: xorl %edx, %edx
410 ; CHECK-NEXT: divl %esi
411 ; CHECK-NEXT: andl %edi, %eax
412 ; CHECK-NEXT: retq
413 %B17 = or i32 0, 2147483647
414 %L6 = load i32, ptr undef
415 %B11 = sdiv i32 %B17, %L6
416 %B13 = udiv i32 %B17, %L6
417 %B14 = srem i32 %B11, %B13
418 %B16 = srem i32 %L6, %B14
419 %B10 = udiv i32 %L6, %B14
420 %B6 = and i32 %B16, %B10
421 ret i32 %B6
422 }
424 define i1 @bool_srem(i1 %x, i1 %y) {
425 ; CHECK-LABEL: bool_srem:
426 ; CHECK: # %bb.0:
427 ; CHECK-NEXT: xorl %eax, %eax
428 ; CHECK-NEXT: retq
429 %r = srem i1 %x, %y
430 ret i1 %r
431 }
432 define <4 x i1> @boolvec_srem(<4 x i1> %x, <4 x i1> %y) {
433 ; SSE-LABEL: boolvec_srem:
434 ; SSE: # %bb.0:
435 ; SSE-NEXT: xorps %xmm0, %xmm0
436 ; SSE-NEXT: retq
437 ;
438 ; AVX-LABEL: boolvec_srem:
439 ; AVX: # %bb.0:
440 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
441 ; AVX-NEXT: retq
442 %r = srem <4 x i1> %x, %y
443 ret <4 x i1> %r
444 }
446 define i32 @combine_srem_two(i32 %x) {
447 ; CHECK-LABEL: combine_srem_two:
448 ; CHECK: # %bb.0:
449 ; CHECK-NEXT: movl %edi, %eax
450 ; CHECK-NEXT: movl %edi, %ecx
451 ; CHECK-NEXT: shrl $31, %ecx
452 ; CHECK-NEXT: addl %edi, %ecx
453 ; CHECK-NEXT: andl $-2, %ecx
454 ; CHECK-NEXT: subl %ecx, %eax
455 ; CHECK-NEXT: retq
456 %1 = srem i32 %x, 2
457 ret i32 %1
458 }
460 define i32 @combine_srem_negtwo(i32 %x) {
461 ; CHECK-LABEL: combine_srem_negtwo:
462 ; CHECK: # %bb.0:
463 ; CHECK-NEXT: movl %edi, %eax
464 ; CHECK-NEXT: movl %edi, %ecx
465 ; CHECK-NEXT: shrl $31, %ecx
466 ; CHECK-NEXT: addl %edi, %ecx
467 ; CHECK-NEXT: andl $-2, %ecx
468 ; CHECK-NEXT: subl %ecx, %eax
469 ; CHECK-NEXT: retq
470 %1 = srem i32 %x, -2
471 ret i32 %1
472 }
474 define i8 @combine_i8_srem_negpow2(i8 %x) {
475 ; CHECK-LABEL: combine_i8_srem_negpow2:
476 ; CHECK: # %bb.0:
477 ; CHECK-NEXT: movl %edi, %eax
478 ; CHECK-NEXT: movl %eax, %ecx
479 ; CHECK-NEXT: sarb $7, %cl
480 ; CHECK-NEXT: shrb $2, %cl
481 ; CHECK-NEXT: addb %al, %cl
482 ; CHECK-NEXT: andb $-64, %cl
483 ; CHECK-NEXT: subb %cl, %al
484 ; CHECK-NEXT: # kill: def $al killed $al killed $eax
485 ; CHECK-NEXT: retq
486 %1 = srem i8 %x, -64
487 ret i8 %1
488 }
490 define i16 @combine_i16_srem_pow2(i16 %x) {
491 ; CHECK-LABEL: combine_i16_srem_pow2:
492 ; CHECK: # %bb.0:
493 ; CHECK-NEXT: movl %edi, %eax
494 ; CHECK-NEXT: leal 15(%rax), %ecx
495 ; CHECK-NEXT: testw %ax, %ax
496 ; CHECK-NEXT: cmovnsl %edi, %ecx
497 ; CHECK-NEXT: andl $-16, %ecx
498 ; CHECK-NEXT: subl %ecx, %eax
499 ; CHECK-NEXT: # kill: def $ax killed $ax killed $rax
500 ; CHECK-NEXT: retq
501 %1 = srem i16 %x, 16
502 ret i16 %1
503 }
505 define i16 @combine_i16_srem_negpow2(i16 %x) {
506 ; CHECK-LABEL: combine_i16_srem_negpow2:
507 ; CHECK: # %bb.0:
508 ; CHECK-NEXT: movl %edi, %eax
509 ; CHECK-NEXT: leal 255(%rax), %ecx
510 ; CHECK-NEXT: testw %ax, %ax
511 ; CHECK-NEXT: cmovnsl %edi, %ecx
512 ; CHECK-NEXT: andl $-256, %ecx
513 ; CHECK-NEXT: subl %ecx, %eax
514 ; CHECK-NEXT: # kill: def $ax killed $ax killed $rax
515 ; CHECK-NEXT: retq
516 %1 = srem i16 %x, -256
517 ret i16 %1
518 }
520 define i32 @combine_srem_pow2(i32 %x) {
521 ; CHECK-LABEL: combine_srem_pow2:
522 ; CHECK: # %bb.0:
523 ; CHECK-NEXT: movl %edi, %eax
524 ; CHECK-NEXT: leal 15(%rax), %ecx
525 ; CHECK-NEXT: testl %edi, %edi
526 ; CHECK-NEXT: cmovnsl %edi, %ecx
527 ; CHECK-NEXT: andl $-16, %ecx
528 ; CHECK-NEXT: subl %ecx, %eax
529 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
530 ; CHECK-NEXT: retq
531 %1 = srem i32 %x, 16
532 ret i32 %1
533 }
535 define i32 @combine_srem_negpow2(i32 %x) {
536 ; CHECK-LABEL: combine_srem_negpow2:
537 ; CHECK: # %bb.0:
538 ; CHECK-NEXT: movl %edi, %eax
539 ; CHECK-NEXT: leal 255(%rax), %ecx
540 ; CHECK-NEXT: testl %edi, %edi
541 ; CHECK-NEXT: cmovnsl %edi, %ecx
542 ; CHECK-NEXT: andl $-256, %ecx
543 ; CHECK-NEXT: subl %ecx, %eax
544 ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
545 ; CHECK-NEXT: retq
546 %1 = srem i32 %x, -256
547 ret i32 %1
548 }
550 define i64 @combine_i64_srem_pow2(i64 %x) {
551 ; CHECK-LABEL: combine_i64_srem_pow2:
552 ; CHECK: # %bb.0:
553 ; CHECK-NEXT: movq %rdi, %rax
554 ; CHECK-NEXT: leaq 15(%rdi), %rcx
555 ; CHECK-NEXT: testq %rdi, %rdi
556 ; CHECK-NEXT: cmovnsq %rdi, %rcx
557 ; CHECK-NEXT: andq $-16, %rcx
558 ; CHECK-NEXT: subq %rcx, %rax
559 ; CHECK-NEXT: retq
560 %1 = srem i64 %x, 16
561 ret i64 %1
562 }
564 define i64 @combine_i64_srem_negpow2(i64 %x) {
565 ; CHECK-LABEL: combine_i64_srem_negpow2:
566 ; CHECK: # %bb.0:
567 ; CHECK-NEXT: movq %rdi, %rax
568 ; CHECK-NEXT: leaq 255(%rdi), %rcx
569 ; CHECK-NEXT: testq %rdi, %rdi
570 ; CHECK-NEXT: cmovnsq %rdi, %rcx
571 ; CHECK-NEXT: andq $-256, %rcx
572 ; CHECK-NEXT: subq %rcx, %rax
573 ; CHECK-NEXT: retq
574 %1 = srem i64 %x, -256
575 ret i64 %1
576 }