| blob | 25d2753480131d89a1b37808307cdc2772587b59 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Darwin
3 ; RUN: llc < %s -mattr=+sse2 -mtriple=i686-pc-mingw32 -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Mingw32
4 ; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
5 ; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE
6 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64
7 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=nehalem | FileCheck %s -check-prefix=NHM_64
9 @.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00"
10 @.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4
12 define void @t1(i32 %argc, ptr %argv) nounwind {
13 ; SSE2-Darwin-LABEL: t1:
14 ; SSE2-Darwin: ## %bb.0: ## %entry
15 ; SSE2-Darwin-NEXT: subl $28, %esp
16 ; SSE2-Darwin-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
17 ; SSE2-Darwin-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
18 ; SSE2-Darwin-NEXT: movaps _.str, %xmm0
19 ; SSE2-Darwin-NEXT: movaps %xmm0, (%esp)
20 ; SSE2-Darwin-NEXT: movb $0, {{[0-9]+}}(%esp)
21 ; SSE2-Darwin-NEXT: ud2
22 ;
23 ; SSE2-Mingw32-LABEL: t1:
24 ; SSE2-Mingw32: # %bb.0: # %entry
25 ; SSE2-Mingw32-NEXT: subl $28, %esp
26 ; SSE2-Mingw32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
27 ; SSE2-Mingw32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
28 ; SSE2-Mingw32-NEXT: movaps _.str, %xmm0
29 ; SSE2-Mingw32-NEXT: movups %xmm0, (%esp)
30 ; SSE2-Mingw32-NEXT: movb $0, {{[0-9]+}}(%esp)
31 ;
32 ; SSE1-LABEL: t1:
33 ; SSE1: ## %bb.0: ## %entry
34 ; SSE1-NEXT: subl $28, %esp
35 ; SSE1-NEXT: movaps _.str, %xmm0
36 ; SSE1-NEXT: movaps %xmm0, (%esp)
37 ; SSE1-NEXT: movb $0, {{[0-9]+}}(%esp)
38 ; SSE1-NEXT: movl $0, {{[0-9]+}}(%esp)
39 ; SSE1-NEXT: movl $0, {{[0-9]+}}(%esp)
40 ; SSE1-NEXT: ud2
41 ;
42 ; NOSSE-LABEL: t1:
43 ; NOSSE: ## %bb.0: ## %entry
44 ; NOSSE-NEXT: subl $28, %esp
45 ; NOSSE-NEXT: movb $0, {{[0-9]+}}(%esp)
46 ; NOSSE-NEXT: movl $0, {{[0-9]+}}(%esp)
47 ; NOSSE-NEXT: movl $0, {{[0-9]+}}(%esp)
48 ; NOSSE-NEXT: movl $0, {{[0-9]+}}(%esp)
49 ; NOSSE-NEXT: movl $0, {{[0-9]+}}(%esp)
50 ; NOSSE-NEXT: movl $101, {{[0-9]+}}(%esp)
51 ; NOSSE-NEXT: movl $1734438249, (%esp) ## imm = 0x67616D69
52 ; NOSSE-NEXT: ud2
53 ;
54 ; X86-64-LABEL: t1:
55 ; X86-64: ## %bb.0: ## %entry
56 ; X86-64-NEXT: movaps _.str(%rip), %xmm0
57 ; X86-64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
58 ; X86-64-NEXT: movb $0, -{{[0-9]+}}(%rsp)
59 ; X86-64-NEXT: movq $0, -{{[0-9]+}}(%rsp)
60 ; X86-64-NEXT: ud2
61 ;
62 ; NHM_64-LABEL: t1:
63 ; NHM_64: ## %bb.0: ## %entry
64 ; NHM_64-NEXT: movups _.str+9(%rip), %xmm0
65 ; NHM_64-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
66 ; NHM_64-NEXT: movaps _.str(%rip), %xmm0
67 ; NHM_64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
68 ; NHM_64-NEXT: ud2
69 entry:
70 %tmp1 = alloca [25 x i8]
71 call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp1, ptr align 1 @.str, i32 25, i1 false)
72 unreachable
73 }
75 ;rdar://7774704
76 %struct.s0 = type { [2 x double] }
78 define void @t2(ptr nocapture %a, ptr nocapture %b) nounwind ssp {
79 ; SSE2-Darwin-LABEL: t2:
80 ; SSE2-Darwin: ## %bb.0: ## %entry
81 ; SSE2-Darwin-NEXT: movl {{[0-9]+}}(%esp), %eax
82 ; SSE2-Darwin-NEXT: movl {{[0-9]+}}(%esp), %ecx
83 ; SSE2-Darwin-NEXT: movaps (%ecx), %xmm0
84 ; SSE2-Darwin-NEXT: movaps %xmm0, (%eax)
85 ; SSE2-Darwin-NEXT: retl
86 ;
87 ; SSE2-Mingw32-LABEL: t2:
88 ; SSE2-Mingw32: # %bb.0: # %entry
89 ; SSE2-Mingw32-NEXT: movl {{[0-9]+}}(%esp), %eax
90 ; SSE2-Mingw32-NEXT: movl {{[0-9]+}}(%esp), %ecx
91 ; SSE2-Mingw32-NEXT: movaps (%ecx), %xmm0
92 ; SSE2-Mingw32-NEXT: movaps %xmm0, (%eax)
93 ; SSE2-Mingw32-NEXT: retl
94 ;
95 ; SSE1-LABEL: t2:
96 ; SSE1: ## %bb.0: ## %entry
97 ; SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
98 ; SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
99 ; SSE1-NEXT: movaps (%ecx), %xmm0
100 ; SSE1-NEXT: movaps %xmm0, (%eax)
101 ; SSE1-NEXT: retl
102 ;
103 ; NOSSE-LABEL: t2:
104 ; NOSSE: ## %bb.0: ## %entry
105 ; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
106 ; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
107 ; NOSSE-NEXT: movl 12(%ecx), %edx
108 ; NOSSE-NEXT: movl %edx, 12(%eax)
109 ; NOSSE-NEXT: movl 8(%ecx), %edx
110 ; NOSSE-NEXT: movl %edx, 8(%eax)
111 ; NOSSE-NEXT: movl (%ecx), %edx
112 ; NOSSE-NEXT: movl 4(%ecx), %ecx
113 ; NOSSE-NEXT: movl %ecx, 4(%eax)
114 ; NOSSE-NEXT: movl %edx, (%eax)
115 ; NOSSE-NEXT: retl
116 ;
117 ; X86-64-LABEL: t2:
118 ; X86-64: ## %bb.0: ## %entry
119 ; X86-64-NEXT: movaps (%rsi), %xmm0
120 ; X86-64-NEXT: movaps %xmm0, (%rdi)
121 ; X86-64-NEXT: retq
122 ;
123 ; NHM_64-LABEL: t2:
124 ; NHM_64: ## %bb.0: ## %entry
125 ; NHM_64-NEXT: movaps (%rsi), %xmm0
126 ; NHM_64-NEXT: movaps %xmm0, (%rdi)
127 ; NHM_64-NEXT: retq
128 entry:
129 tail call void @llvm.memcpy.p0.p0.i32(ptr align 16 %a, ptr align 16 %b, i32 16, i1 false)
130 ret void
131 }
133 define void @t3(ptr nocapture %a, ptr nocapture %b) nounwind ssp {
134 ; SSE2-Darwin-LABEL: t3:
135 ; SSE2-Darwin: ## %bb.0: ## %entry
136 ; SSE2-Darwin-NEXT: movl {{[0-9]+}}(%esp), %eax
137 ; SSE2-Darwin-NEXT: movl {{[0-9]+}}(%esp), %ecx
138 ; SSE2-Darwin-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
139 ; SSE2-Darwin-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
140 ; SSE2-Darwin-NEXT: movsd %xmm1, 8(%eax)
141 ; SSE2-Darwin-NEXT: movsd %xmm0, (%eax)
142 ; SSE2-Darwin-NEXT: retl
143 ;
144 ; SSE2-Mingw32-LABEL: t3:
145 ; SSE2-Mingw32: # %bb.0: # %entry
146 ; SSE2-Mingw32-NEXT: movl {{[0-9]+}}(%esp), %eax
147 ; SSE2-Mingw32-NEXT: movl {{[0-9]+}}(%esp), %ecx
148 ; SSE2-Mingw32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
149 ; SSE2-Mingw32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
150 ; SSE2-Mingw32-NEXT: movsd %xmm1, 8(%eax)
151 ; SSE2-Mingw32-NEXT: movsd %xmm0, (%eax)
152 ; SSE2-Mingw32-NEXT: retl
153 ;
154 ; SSE1-LABEL: t3:
155 ; SSE1: ## %bb.0: ## %entry
156 ; SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
157 ; SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
158 ; SSE1-NEXT: movl 12(%ecx), %edx
159 ; SSE1-NEXT: movl %edx, 12(%eax)
160 ; SSE1-NEXT: movl 8(%ecx), %edx
161 ; SSE1-NEXT: movl %edx, 8(%eax)
162 ; SSE1-NEXT: movl (%ecx), %edx
163 ; SSE1-NEXT: movl 4(%ecx), %ecx
164 ; SSE1-NEXT: movl %ecx, 4(%eax)
165 ; SSE1-NEXT: movl %edx, (%eax)
166 ; SSE1-NEXT: retl
167 ;
168 ; NOSSE-LABEL: t3:
169 ; NOSSE: ## %bb.0: ## %entry
170 ; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
171 ; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
172 ; NOSSE-NEXT: movl 12(%ecx), %edx
173 ; NOSSE-NEXT: movl %edx, 12(%eax)
174 ; NOSSE-NEXT: movl 8(%ecx), %edx
175 ; NOSSE-NEXT: movl %edx, 8(%eax)
176 ; NOSSE-NEXT: movl (%ecx), %edx
177 ; NOSSE-NEXT: movl 4(%ecx), %ecx
178 ; NOSSE-NEXT: movl %ecx, 4(%eax)
179 ; NOSSE-NEXT: movl %edx, (%eax)
180 ; NOSSE-NEXT: retl
181 ;
182 ; X86-64-LABEL: t3:
183 ; X86-64: ## %bb.0: ## %entry
184 ; X86-64-NEXT: movq (%rsi), %rax
185 ; X86-64-NEXT: movq 8(%rsi), %rcx
186 ; X86-64-NEXT: movq %rcx, 8(%rdi)
187 ; X86-64-NEXT: movq %rax, (%rdi)
188 ; X86-64-NEXT: retq
189 ;
190 ; NHM_64-LABEL: t3:
191 ; NHM_64: ## %bb.0: ## %entry
192 ; NHM_64-NEXT: movups (%rsi), %xmm0
193 ; NHM_64-NEXT: movups %xmm0, (%rdi)
194 ; NHM_64-NEXT: retq
195 entry:
196 tail call void @llvm.memcpy.p0.p0.i32(ptr align 8 %a, ptr align 8 %b, i32 16, i1 false)
197 ret void
198 }
200 ;;; TODO: (1) Some of the loads and stores are certainly unaligned and (2) the first load and first
201 ;;; store overlap with the second load and second store respectively.
202 ;;;
203 ;;; Are any of the sequences ideal?
204 define void @t4() nounwind {
205 ; SSE2-Darwin-LABEL: t4:
206 ; SSE2-Darwin: ## %bb.0: ## %entry
207 ; SSE2-Darwin-NEXT: subl $32, %esp
208 ; SSE2-Darwin-NEXT: movw $120, {{[0-9]+}}(%esp)
209 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
210 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
211 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
212 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
213 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
214 ; SSE2-Darwin-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
215 ; SSE2-Darwin-NEXT: movl $2021161080, (%esp) ## imm = 0x78787878
216 ; SSE2-Darwin-NEXT: ud2
217 ;
218 ; SSE2-Mingw32-LABEL: t4:
219 ; SSE2-Mingw32: # %bb.0: # %entry
220 ; SSE2-Mingw32-NEXT: subl $32, %esp
221 ; SSE2-Mingw32-NEXT: movw $120, {{[0-9]+}}(%esp)
222 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
223 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
224 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
225 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
226 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
227 ; SSE2-Mingw32-NEXT: movl $2021161080, {{[0-9]+}}(%esp) # imm = 0x78787878
228 ; SSE2-Mingw32-NEXT: movl $2021161080, (%esp) # imm = 0x78787878
229 ;
230 ; SSE1-LABEL: t4:
231 ; SSE1: ## %bb.0: ## %entry
232 ; SSE1-NEXT: subl $32, %esp
233 ; SSE1-NEXT: movw $120, {{[0-9]+}}(%esp)
234 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
235 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
236 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
237 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
238 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
239 ; SSE1-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
240 ; SSE1-NEXT: movl $2021161080, (%esp) ## imm = 0x78787878
241 ; SSE1-NEXT: ud2
242 ;
243 ; NOSSE-LABEL: t4:
244 ; NOSSE: ## %bb.0: ## %entry
245 ; NOSSE-NEXT: subl $32, %esp
246 ; NOSSE-NEXT: movw $120, {{[0-9]+}}(%esp)
247 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
248 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
249 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
250 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
251 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
252 ; NOSSE-NEXT: movl $2021161080, {{[0-9]+}}(%esp) ## imm = 0x78787878
253 ; NOSSE-NEXT: movl $2021161080, (%esp) ## imm = 0x78787878
254 ; NOSSE-NEXT: ud2
255 ;
256 ; X86-64-LABEL: t4:
257 ; X86-64: ## %bb.0: ## %entry
258 ; X86-64-NEXT: movabsq $33909456017848440, %rax ## imm = 0x78787878787878
259 ; X86-64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
260 ; X86-64-NEXT: movabsq $8680820740569200760, %rax ## imm = 0x7878787878787878
261 ; X86-64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
262 ; X86-64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
263 ; X86-64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
264 ; X86-64-NEXT: ud2
265 ;
266 ; NHM_64-LABEL: t4:
267 ; NHM_64: ## %bb.0: ## %entry
268 ; NHM_64-NEXT: movups _.str2+14(%rip), %xmm0
269 ; NHM_64-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
270 ; NHM_64-NEXT: movups _.str2(%rip), %xmm0
271 ; NHM_64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
272 ; NHM_64-NEXT: ud2
273 entry:
274 %tmp1 = alloca [30 x i8]
275 call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp1, ptr align 1 @.str2, i32 30, i1 false)
276 unreachable
277 }
279 declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind