| blob | 24113441a4e25a87945bf8e7f637f383cee95306 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512F
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512FP16
10 ;
11 ; vXf32
12 ;
14 define float @test_v1f32(<1 x float> %a0) {
15 ; ALL-LABEL: test_v1f32:
16 ; ALL: # %bb.0:
17 ; ALL-NEXT: retq
18 %1 = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a0)
19 ret float %1
20 }
22 define float @test_v2f32(<2 x float> %a0) {
23 ; SSE2-LABEL: test_v2f32:
24 ; SSE2: # %bb.0:
25 ; SSE2-NEXT: movaps %xmm0, %xmm1
26 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
27 ; SSE2-NEXT: maxss %xmm1, %xmm0
28 ; SSE2-NEXT: retq
29 ;
30 ; SSE41-LABEL: test_v2f32:
31 ; SSE41: # %bb.0:
32 ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
33 ; SSE41-NEXT: maxss %xmm1, %xmm0
34 ; SSE41-NEXT: retq
35 ;
36 ; AVX-LABEL: test_v2f32:
37 ; AVX: # %bb.0:
38 ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
39 ; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
40 ; AVX-NEXT: retq
41 ;
42 ; AVX512-LABEL: test_v2f32:
43 ; AVX512: # %bb.0:
44 ; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
45 ; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
46 ; AVX512-NEXT: retq
47 %1 = call nnan float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a0)
48 ret float %1
49 }
51 define float @test_v4f32(<4 x float> %a0) {
52 ; SSE2-LABEL: test_v4f32:
53 ; SSE2: # %bb.0:
54 ; SSE2-NEXT: movaps %xmm0, %xmm1
55 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
56 ; SSE2-NEXT: maxps %xmm1, %xmm0
57 ; SSE2-NEXT: movaps %xmm0, %xmm1
58 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
59 ; SSE2-NEXT: maxss %xmm1, %xmm0
60 ; SSE2-NEXT: retq
61 ;
62 ; SSE41-LABEL: test_v4f32:
63 ; SSE41: # %bb.0:
64 ; SSE41-NEXT: movaps %xmm0, %xmm1
65 ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
66 ; SSE41-NEXT: maxps %xmm1, %xmm0
67 ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
68 ; SSE41-NEXT: maxss %xmm1, %xmm0
69 ; SSE41-NEXT: retq
70 ;
71 ; AVX-LABEL: test_v4f32:
72 ; AVX: # %bb.0:
73 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
74 ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
75 ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
76 ; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
77 ; AVX-NEXT: retq
78 ;
79 ; AVX512-LABEL: test_v4f32:
80 ; AVX512: # %bb.0:
81 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
82 ; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0
83 ; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
84 ; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
85 ; AVX512-NEXT: retq
86 %1 = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0)
87 ret float %1
88 }
90 define float @test_v8f32(<8 x float> %a0) {
91 ; SSE2-LABEL: test_v8f32:
92 ; SSE2: # %bb.0:
93 ; SSE2-NEXT: maxps %xmm1, %xmm0
94 ; SSE2-NEXT: movaps %xmm0, %xmm1
95 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
96 ; SSE2-NEXT: maxps %xmm1, %xmm0
97 ; SSE2-NEXT: movaps %xmm0, %xmm1
98 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
99 ; SSE2-NEXT: maxss %xmm1, %xmm0
100 ; SSE2-NEXT: retq
101 ;
102 ; SSE41-LABEL: test_v8f32:
103 ; SSE41: # %bb.0:
104 ; SSE41-NEXT: maxps %xmm1, %xmm0
105 ; SSE41-NEXT: movaps %xmm0, %xmm1
106 ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
107 ; SSE41-NEXT: maxps %xmm1, %xmm0
108 ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
109 ; SSE41-NEXT: maxss %xmm1, %xmm0
110 ; SSE41-NEXT: retq
111 ;
112 ; AVX-LABEL: test_v8f32:
113 ; AVX: # %bb.0:
114 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
115 ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
116 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
117 ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
118 ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
119 ; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
120 ; AVX-NEXT: vzeroupper
121 ; AVX-NEXT: retq
122 ;
123 ; AVX512-LABEL: test_v8f32:
124 ; AVX512: # %bb.0:
125 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
126 ; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0
127 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
128 ; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0
129 ; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
130 ; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
131 ; AVX512-NEXT: vzeroupper
132 ; AVX512-NEXT: retq
133 %1 = call nnan float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a0)
134 ret float %1
135 }
137 define float @test_v16f32(<16 x float> %a0) {
138 ; SSE2-LABEL: test_v16f32:
139 ; SSE2: # %bb.0:
140 ; SSE2-NEXT: maxps %xmm3, %xmm1
141 ; SSE2-NEXT: maxps %xmm2, %xmm0
142 ; SSE2-NEXT: maxps %xmm1, %xmm0
143 ; SSE2-NEXT: movaps %xmm0, %xmm1
144 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
145 ; SSE2-NEXT: maxps %xmm1, %xmm0
146 ; SSE2-NEXT: movaps %xmm0, %xmm1
147 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
148 ; SSE2-NEXT: maxss %xmm1, %xmm0
149 ; SSE2-NEXT: retq
150 ;
151 ; SSE41-LABEL: test_v16f32:
152 ; SSE41: # %bb.0:
153 ; SSE41-NEXT: maxps %xmm3, %xmm1
154 ; SSE41-NEXT: maxps %xmm2, %xmm0
155 ; SSE41-NEXT: maxps %xmm1, %xmm0
156 ; SSE41-NEXT: movaps %xmm0, %xmm1
157 ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
158 ; SSE41-NEXT: maxps %xmm1, %xmm0
159 ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
160 ; SSE41-NEXT: maxss %xmm1, %xmm0
161 ; SSE41-NEXT: retq
162 ;
163 ; AVX-LABEL: test_v16f32:
164 ; AVX: # %bb.0:
165 ; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0
166 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
167 ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
168 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
169 ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
170 ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
171 ; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
172 ; AVX-NEXT: vzeroupper
173 ; AVX-NEXT: retq
174 ;
175 ; AVX512-LABEL: test_v16f32:
176 ; AVX512: # %bb.0:
177 ; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1
178 ; AVX512-NEXT: vmaxps %zmm1, %zmm0, %zmm0
179 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
180 ; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0
181 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
182 ; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0
183 ; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
184 ; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0
185 ; AVX512-NEXT: vzeroupper
186 ; AVX512-NEXT: retq
187 %1 = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a0)
188 ret float %1
189 }
191 ;
192 ; vXf64
193 ;
195 define double @test_v2f64(<2 x double> %a0) {
196 ; SSE-LABEL: test_v2f64:
197 ; SSE: # %bb.0:
198 ; SSE-NEXT: movapd %xmm0, %xmm1
199 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
200 ; SSE-NEXT: maxsd %xmm1, %xmm0
201 ; SSE-NEXT: retq
202 ;
203 ; AVX-LABEL: test_v2f64:
204 ; AVX: # %bb.0:
205 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
206 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
207 ; AVX-NEXT: retq
208 ;
209 ; AVX512-LABEL: test_v2f64:
210 ; AVX512: # %bb.0:
211 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
212 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
213 ; AVX512-NEXT: retq
214 %1 = call nnan double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a0)
215 ret double %1
216 }
218 define double @test_v3f64(<3 x double> %a0) {
219 ; SSE2-LABEL: test_v3f64:
220 ; SSE2: # %bb.0:
221 ; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
222 ; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1]
223 ; SSE2-NEXT: maxpd %xmm2, %xmm0
224 ; SSE2-NEXT: movapd %xmm0, %xmm1
225 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
226 ; SSE2-NEXT: maxsd %xmm1, %xmm0
227 ; SSE2-NEXT: retq
228 ;
229 ; SSE41-LABEL: test_v3f64:
230 ; SSE41: # %bb.0:
231 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
232 ; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]
233 ; SSE41-NEXT: maxpd %xmm2, %xmm0
234 ; SSE41-NEXT: movapd %xmm0, %xmm1
235 ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
236 ; SSE41-NEXT: maxsd %xmm1, %xmm0
237 ; SSE41-NEXT: retq
238 ;
239 ; AVX-LABEL: test_v3f64:
240 ; AVX: # %bb.0:
241 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
242 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
243 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
244 ; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
245 ; AVX-NEXT: vzeroupper
246 ; AVX-NEXT: retq
247 ;
248 ; AVX512-LABEL: test_v3f64:
249 ; AVX512: # %bb.0:
250 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
251 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
252 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
253 ; AVX512-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
254 ; AVX512-NEXT: vzeroupper
255 ; AVX512-NEXT: retq
256 %1 = call nnan double @llvm.vector.reduce.fmax.v3f64(<3 x double> %a0)
257 ret double %1
258 }
260 define double @test_v4f64(<4 x double> %a0) {
261 ; SSE-LABEL: test_v4f64:
262 ; SSE: # %bb.0:
263 ; SSE-NEXT: maxpd %xmm1, %xmm0
264 ; SSE-NEXT: movapd %xmm0, %xmm1
265 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
266 ; SSE-NEXT: maxsd %xmm1, %xmm0
267 ; SSE-NEXT: retq
268 ;
269 ; AVX-LABEL: test_v4f64:
270 ; AVX: # %bb.0:
271 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
272 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
273 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
274 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
275 ; AVX-NEXT: vzeroupper
276 ; AVX-NEXT: retq
277 ;
278 ; AVX512-LABEL: test_v4f64:
279 ; AVX512: # %bb.0:
280 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
281 ; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
282 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
283 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
284 ; AVX512-NEXT: vzeroupper
285 ; AVX512-NEXT: retq
286 %1 = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a0)
287 ret double %1
288 }
290 define double @test_v8f64(<8 x double> %a0) {
291 ; SSE-LABEL: test_v8f64:
292 ; SSE: # %bb.0:
293 ; SSE-NEXT: maxpd %xmm3, %xmm1
294 ; SSE-NEXT: maxpd %xmm2, %xmm0
295 ; SSE-NEXT: maxpd %xmm1, %xmm0
296 ; SSE-NEXT: movapd %xmm0, %xmm1
297 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
298 ; SSE-NEXT: maxsd %xmm1, %xmm0
299 ; SSE-NEXT: retq
300 ;
301 ; AVX-LABEL: test_v8f64:
302 ; AVX: # %bb.0:
303 ; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
304 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
305 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
306 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
307 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
308 ; AVX-NEXT: vzeroupper
309 ; AVX-NEXT: retq
310 ;
311 ; AVX512-LABEL: test_v8f64:
312 ; AVX512: # %bb.0:
313 ; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1
314 ; AVX512-NEXT: vmaxpd %zmm1, %zmm0, %zmm0
315 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
316 ; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
317 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
318 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
319 ; AVX512-NEXT: vzeroupper
320 ; AVX512-NEXT: retq
321 %1 = call nnan double @llvm.vector.reduce.fmax.v8f64(<8 x double> %a0)
322 ret double %1
323 }
325 define double @test_v16f64(<16 x double> %a0) {
326 ; SSE-LABEL: test_v16f64:
327 ; SSE: # %bb.0:
328 ; SSE-NEXT: maxpd %xmm6, %xmm2
329 ; SSE-NEXT: maxpd %xmm4, %xmm0
330 ; SSE-NEXT: maxpd %xmm2, %xmm0
331 ; SSE-NEXT: maxpd %xmm7, %xmm3
332 ; SSE-NEXT: maxpd %xmm5, %xmm1
333 ; SSE-NEXT: maxpd %xmm3, %xmm1
334 ; SSE-NEXT: maxpd %xmm1, %xmm0
335 ; SSE-NEXT: movapd %xmm0, %xmm1
336 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
337 ; SSE-NEXT: maxsd %xmm1, %xmm0
338 ; SSE-NEXT: retq
339 ;
340 ; AVX-LABEL: test_v16f64:
341 ; AVX: # %bb.0:
342 ; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1
343 ; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0
344 ; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
345 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
346 ; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
347 ; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
348 ; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
349 ; AVX-NEXT: vzeroupper
350 ; AVX-NEXT: retq
351 ;
352 ; AVX512-LABEL: test_v16f64:
353 ; AVX512: # %bb.0:
354 ; AVX512-NEXT: vmaxpd %zmm1, %zmm0, %zmm0
355 ; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1
356 ; AVX512-NEXT: vmaxpd %zmm1, %zmm0, %zmm0
357 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
358 ; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
359 ; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
360 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
361 ; AVX512-NEXT: vzeroupper
362 ; AVX512-NEXT: retq
363 %1 = call nnan double @llvm.vector.reduce.fmax.v16f64(<16 x double> %a0)
364 ret double %1
365 }
367 define half @test_v2f16(<2 x half> %a0) nounwind {
368 ; SSE-LABEL: test_v2f16:
369 ; SSE: # %bb.0:
370 ; SSE-NEXT: pushq %rbp
371 ; SSE-NEXT: pushq %rbx
372 ; SSE-NEXT: subq $40, %rsp
373 ; SSE-NEXT: movdqa %xmm0, %xmm1
374 ; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
375 ; SSE-NEXT: psrld $16, %xmm0
376 ; SSE-NEXT: pextrw $0, %xmm0, %ebx
377 ; SSE-NEXT: pextrw $0, %xmm1, %ebp
378 ; SSE-NEXT: callq __extendhfsf2@PLT
379 ; SSE-NEXT: movd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
380 ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
381 ; SSE-NEXT: callq __extendhfsf2@PLT
382 ; SSE-NEXT: ucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload
383 ; SSE-NEXT: cmoval %ebp, %ebx
384 ; SSE-NEXT: pinsrw $0, %ebx, %xmm0
385 ; SSE-NEXT: addq $40, %rsp
386 ; SSE-NEXT: popq %rbx
387 ; SSE-NEXT: popq %rbp
388 ; SSE-NEXT: retq
389 ;
390 ; AVX-LABEL: test_v2f16:
391 ; AVX: # %bb.0:
392 ; AVX-NEXT: pushq %rbp
393 ; AVX-NEXT: pushq %rbx
394 ; AVX-NEXT: subq $40, %rsp
395 ; AVX-NEXT: vmovdqa %xmm0, %xmm1
396 ; AVX-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
397 ; AVX-NEXT: vpsrld $16, %xmm0, %xmm0
398 ; AVX-NEXT: vpextrw $0, %xmm0, %ebx
399 ; AVX-NEXT: vpextrw $0, %xmm1, %ebp
400 ; AVX-NEXT: callq __extendhfsf2@PLT
401 ; AVX-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill
402 ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
403 ; AVX-NEXT: callq __extendhfsf2@PLT
404 ; AVX-NEXT: vucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload
405 ; AVX-NEXT: cmoval %ebp, %ebx
406 ; AVX-NEXT: vpinsrw $0, %ebx, %xmm0, %xmm0
407 ; AVX-NEXT: addq $40, %rsp
408 ; AVX-NEXT: popq %rbx
409 ; AVX-NEXT: popq %rbp
410 ; AVX-NEXT: retq
411 ;
412 ; AVX512F-LABEL: test_v2f16:
413 ; AVX512F: # %bb.0:
414 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
415 ; AVX512F-NEXT: vpsrld $16, %xmm0, %xmm1
416 ; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm2
417 ; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm3
418 ; AVX512F-NEXT: xorl %eax, %eax
419 ; AVX512F-NEXT: vucomiss %xmm3, %xmm2
420 ; AVX512F-NEXT: movl $255, %ecx
421 ; AVX512F-NEXT: cmovbel %eax, %ecx
422 ; AVX512F-NEXT: kmovd %ecx, %k1
423 ; AVX512F-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1}
424 ; AVX512F-NEXT: vmovdqa %xmm1, %xmm0
425 ; AVX512F-NEXT: vzeroupper
426 ; AVX512F-NEXT: retq
427 ;
428 ; AVX512VL-LABEL: test_v2f16:
429 ; AVX512VL: # %bb.0:
430 ; AVX512VL-NEXT: vpsrld $16, %xmm0, %xmm1
431 ; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm2
432 ; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm3
433 ; AVX512VL-NEXT: xorl %eax, %eax
434 ; AVX512VL-NEXT: vucomiss %xmm3, %xmm2
435 ; AVX512VL-NEXT: movl $255, %ecx
436 ; AVX512VL-NEXT: cmovbel %eax, %ecx
437 ; AVX512VL-NEXT: kmovd %ecx, %k1
438 ; AVX512VL-NEXT: vmovdqu16 %xmm0, %xmm1 {%k1}
439 ; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0
440 ; AVX512VL-NEXT: retq
441 ;
442 ; AVX512FP16-LABEL: test_v2f16:
443 ; AVX512FP16: # %bb.0:
444 ; AVX512FP16-NEXT: vpsrld $16, %xmm0, %xmm1
445 ; AVX512FP16-NEXT: vcmpltph %xmm0, %xmm1, %k1
446 ; AVX512FP16-NEXT: vmovsh %xmm0, %xmm0, %xmm1 {%k1}
447 ; AVX512FP16-NEXT: vmovaps %xmm1, %xmm0
448 ; AVX512FP16-NEXT: retq
449 %1 = call nnan half @llvm.vector.reduce.fmax.v2f16(<2 x half> %a0)
450 ret half %1
451 }
452 declare float @llvm.vector.reduce.fmax.v1f32(<1 x float>)
453 declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
454 declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
455 declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)
456 declare float @llvm.vector.reduce.fmax.v16f32(<16 x float>)
458 declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
459 declare double @llvm.vector.reduce.fmax.v3f64(<3 x double>)
460 declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
461 declare double @llvm.vector.reduce.fmax.v8f64(<8 x double>)
462 declare double @llvm.vector.reduce.fmax.v16f64(<16 x double>)
464 declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)