| blob | f11b46c62438b9c488d69dcbeee44335f450081f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefixes=XOP,XOPAVX1
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=XOP,XOPAVX2
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX512,AVX512DQ
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW
10 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX512VL,AVX512DQVL
11 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512VL,AVX512BWVL
12 ;
13 ; Just one 32-bit run to make sure we do reasonable things for i64 shifts.
14 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
16 ;
17 ; Variable Shifts
18 ;
20 define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
21 ; SSE2-LABEL: var_shift_v2i64:
22 ; SSE2: # %bb.0:
23 ; SSE2-NEXT: movdqa %xmm0, %xmm2
24 ; SSE2-NEXT: psllq %xmm1, %xmm2
25 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
26 ; SSE2-NEXT: psllq %xmm1, %xmm0
27 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
28 ; SSE2-NEXT: retq
29 ;
30 ; SSE41-LABEL: var_shift_v2i64:
31 ; SSE41: # %bb.0:
32 ; SSE41-NEXT: movdqa %xmm0, %xmm2
33 ; SSE41-NEXT: psllq %xmm1, %xmm2
34 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
35 ; SSE41-NEXT: psllq %xmm1, %xmm0
36 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
37 ; SSE41-NEXT: retq
38 ;
39 ; AVX1-LABEL: var_shift_v2i64:
40 ; AVX1: # %bb.0:
41 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
42 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
43 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
44 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
45 ; AVX1-NEXT: retq
46 ;
47 ; AVX2-LABEL: var_shift_v2i64:
48 ; AVX2: # %bb.0:
49 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
50 ; AVX2-NEXT: retq
51 ;
52 ; XOPAVX1-LABEL: var_shift_v2i64:
53 ; XOPAVX1: # %bb.0:
54 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
55 ; XOPAVX1-NEXT: retq
56 ;
57 ; XOPAVX2-LABEL: var_shift_v2i64:
58 ; XOPAVX2: # %bb.0:
59 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
60 ; XOPAVX2-NEXT: retq
61 ;
62 ; AVX512-LABEL: var_shift_v2i64:
63 ; AVX512: # %bb.0:
64 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
65 ; AVX512-NEXT: retq
66 ;
67 ; AVX512VL-LABEL: var_shift_v2i64:
68 ; AVX512VL: # %bb.0:
69 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
70 ; AVX512VL-NEXT: retq
71 ;
72 ; X86-SSE-LABEL: var_shift_v2i64:
73 ; X86-SSE: # %bb.0:
74 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
75 ; X86-SSE-NEXT: psllq %xmm1, %xmm2
76 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
77 ; X86-SSE-NEXT: psllq %xmm1, %xmm0
78 ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
79 ; X86-SSE-NEXT: retl
80 %shift = shl <2 x i64> %a, %b
81 ret <2 x i64> %shift
82 }
84 define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
85 ; SSE2-LABEL: var_shift_v4i32:
86 ; SSE2: # %bb.0:
87 ; SSE2-NEXT: pslld $23, %xmm1
88 ; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
89 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
90 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
91 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
92 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
93 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
94 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
95 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
96 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
97 ; SSE2-NEXT: retq
98 ;
99 ; SSE41-LABEL: var_shift_v4i32:
100 ; SSE41: # %bb.0:
101 ; SSE41-NEXT: pslld $23, %xmm1
102 ; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
103 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
104 ; SSE41-NEXT: pmulld %xmm1, %xmm0
105 ; SSE41-NEXT: retq
106 ;
107 ; AVX1-LABEL: var_shift_v4i32:
108 ; AVX1: # %bb.0:
109 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
110 ; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
111 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
112 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
113 ; AVX1-NEXT: retq
114 ;
115 ; AVX2-LABEL: var_shift_v4i32:
116 ; AVX2: # %bb.0:
117 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
118 ; AVX2-NEXT: retq
119 ;
120 ; XOPAVX1-LABEL: var_shift_v4i32:
121 ; XOPAVX1: # %bb.0:
122 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
123 ; XOPAVX1-NEXT: retq
124 ;
125 ; XOPAVX2-LABEL: var_shift_v4i32:
126 ; XOPAVX2: # %bb.0:
127 ; XOPAVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
128 ; XOPAVX2-NEXT: retq
129 ;
130 ; AVX512-LABEL: var_shift_v4i32:
131 ; AVX512: # %bb.0:
132 ; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
133 ; AVX512-NEXT: retq
134 ;
135 ; AVX512VL-LABEL: var_shift_v4i32:
136 ; AVX512VL: # %bb.0:
137 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
138 ; AVX512VL-NEXT: retq
139 ;
140 ; X86-SSE-LABEL: var_shift_v4i32:
141 ; X86-SSE: # %bb.0:
142 ; X86-SSE-NEXT: pslld $23, %xmm1
143 ; X86-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
144 ; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1
145 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
146 ; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
147 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
148 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
149 ; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
150 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
151 ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
152 ; X86-SSE-NEXT: retl
153 %shift = shl <4 x i32> %a, %b
154 ret <4 x i32> %shift
155 }
157 define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
158 ; SSE2-LABEL: var_shift_v8i16:
159 ; SSE2: # %bb.0:
160 ; SSE2-NEXT: movdqa %xmm1, %xmm2
161 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
162 ; SSE2-NEXT: pslld $23, %xmm2
163 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
164 ; SSE2-NEXT: paddd %xmm3, %xmm2
165 ; SSE2-NEXT: cvttps2dq %xmm2, %xmm2
166 ; SSE2-NEXT: pslld $16, %xmm2
167 ; SSE2-NEXT: psrad $16, %xmm2
168 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
169 ; SSE2-NEXT: pslld $23, %xmm1
170 ; SSE2-NEXT: paddd %xmm3, %xmm1
171 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
172 ; SSE2-NEXT: pslld $16, %xmm1
173 ; SSE2-NEXT: psrad $16, %xmm1
174 ; SSE2-NEXT: packssdw %xmm2, %xmm1
175 ; SSE2-NEXT: pmullw %xmm1, %xmm0
176 ; SSE2-NEXT: retq
177 ;
178 ; SSE41-LABEL: var_shift_v8i16:
179 ; SSE41: # %bb.0:
180 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
181 ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
182 ; SSE41-NEXT: pslld $23, %xmm1
183 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
184 ; SSE41-NEXT: paddd %xmm3, %xmm1
185 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
186 ; SSE41-NEXT: pslld $23, %xmm2
187 ; SSE41-NEXT: paddd %xmm3, %xmm2
188 ; SSE41-NEXT: cvttps2dq %xmm2, %xmm2
189 ; SSE41-NEXT: packusdw %xmm1, %xmm2
190 ; SSE41-NEXT: pmullw %xmm2, %xmm0
191 ; SSE41-NEXT: retq
192 ;
193 ; AVX1-LABEL: var_shift_v8i16:
194 ; AVX1: # %bb.0:
195 ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4,4,5,5,6,6,7,7]
196 ; AVX1-NEXT: vpslld $23, %xmm2, %xmm2
197 ; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
198 ; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
199 ; AVX1-NEXT: vcvttps2dq %xmm2, %xmm2
200 ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
201 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
202 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
203 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
204 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
205 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
206 ; AVX1-NEXT: retq
207 ;
208 ; AVX2-LABEL: var_shift_v8i16:
209 ; AVX2: # %bb.0:
210 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
211 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
212 ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
213 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]
214 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
215 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
216 ; AVX2-NEXT: vzeroupper
217 ; AVX2-NEXT: retq
218 ;
219 ; XOP-LABEL: var_shift_v8i16:
220 ; XOP: # %bb.0:
221 ; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
222 ; XOP-NEXT: retq
223 ;
224 ; AVX512DQ-LABEL: var_shift_v8i16:
225 ; AVX512DQ: # %bb.0:
226 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
227 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
228 ; AVX512DQ-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
229 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
230 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
231 ; AVX512DQ-NEXT: vzeroupper
232 ; AVX512DQ-NEXT: retq
233 ;
234 ; AVX512BW-LABEL: var_shift_v8i16:
235 ; AVX512BW: # %bb.0:
236 ; AVX512BW-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
237 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
238 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
239 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
240 ; AVX512BW-NEXT: vzeroupper
241 ; AVX512BW-NEXT: retq
242 ;
243 ; AVX512DQVL-LABEL: var_shift_v8i16:
244 ; AVX512DQVL: # %bb.0:
245 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
246 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
247 ; AVX512DQVL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
248 ; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
249 ; AVX512DQVL-NEXT: vzeroupper
250 ; AVX512DQVL-NEXT: retq
251 ;
252 ; AVX512BWVL-LABEL: var_shift_v8i16:
253 ; AVX512BWVL: # %bb.0:
254 ; AVX512BWVL-NEXT: vpsllvw %xmm1, %xmm0, %xmm0
255 ; AVX512BWVL-NEXT: retq
256 ;
257 ; X86-SSE-LABEL: var_shift_v8i16:
258 ; X86-SSE: # %bb.0:
259 ; X86-SSE-NEXT: movdqa %xmm1, %xmm2
260 ; X86-SSE-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
261 ; X86-SSE-NEXT: pslld $23, %xmm2
262 ; X86-SSE-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
263 ; X86-SSE-NEXT: paddd %xmm3, %xmm2
264 ; X86-SSE-NEXT: cvttps2dq %xmm2, %xmm2
265 ; X86-SSE-NEXT: pslld $16, %xmm2
266 ; X86-SSE-NEXT: psrad $16, %xmm2
267 ; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
268 ; X86-SSE-NEXT: pslld $23, %xmm1
269 ; X86-SSE-NEXT: paddd %xmm3, %xmm1
270 ; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1
271 ; X86-SSE-NEXT: pslld $16, %xmm1
272 ; X86-SSE-NEXT: psrad $16, %xmm1
273 ; X86-SSE-NEXT: packssdw %xmm2, %xmm1
274 ; X86-SSE-NEXT: pmullw %xmm1, %xmm0
275 ; X86-SSE-NEXT: retl
276 %shift = shl <8 x i16> %a, %b
277 ret <8 x i16> %shift
278 }
280 define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
281 ; SSE2-LABEL: var_shift_v16i8:
282 ; SSE2: # %bb.0:
283 ; SSE2-NEXT: psllw $5, %xmm1
284 ; SSE2-NEXT: pxor %xmm2, %xmm2
285 ; SSE2-NEXT: pxor %xmm3, %xmm3
286 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm3
287 ; SSE2-NEXT: movdqa %xmm3, %xmm4
288 ; SSE2-NEXT: pandn %xmm0, %xmm4
289 ; SSE2-NEXT: psllw $4, %xmm0
290 ; SSE2-NEXT: pand %xmm3, %xmm0
291 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
292 ; SSE2-NEXT: por %xmm4, %xmm0
293 ; SSE2-NEXT: paddb %xmm1, %xmm1
294 ; SSE2-NEXT: pxor %xmm3, %xmm3
295 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm3
296 ; SSE2-NEXT: movdqa %xmm3, %xmm4
297 ; SSE2-NEXT: pandn %xmm0, %xmm4
298 ; SSE2-NEXT: psllw $2, %xmm0
299 ; SSE2-NEXT: pand %xmm3, %xmm0
300 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
301 ; SSE2-NEXT: por %xmm4, %xmm0
302 ; SSE2-NEXT: paddb %xmm1, %xmm1
303 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
304 ; SSE2-NEXT: movdqa %xmm2, %xmm1
305 ; SSE2-NEXT: pandn %xmm0, %xmm1
306 ; SSE2-NEXT: paddb %xmm0, %xmm0
307 ; SSE2-NEXT: pand %xmm2, %xmm0
308 ; SSE2-NEXT: por %xmm1, %xmm0
309 ; SSE2-NEXT: retq
310 ;
311 ; SSE41-LABEL: var_shift_v16i8:
312 ; SSE41: # %bb.0:
313 ; SSE41-NEXT: movdqa %xmm0, %xmm2
314 ; SSE41-NEXT: psllw $5, %xmm1
315 ; SSE41-NEXT: movdqa %xmm0, %xmm3
316 ; SSE41-NEXT: psllw $4, %xmm3
317 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
318 ; SSE41-NEXT: movdqa %xmm1, %xmm0
319 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
320 ; SSE41-NEXT: movdqa %xmm2, %xmm3
321 ; SSE41-NEXT: psllw $2, %xmm3
322 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
323 ; SSE41-NEXT: paddb %xmm1, %xmm1
324 ; SSE41-NEXT: movdqa %xmm1, %xmm0
325 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
326 ; SSE41-NEXT: movdqa %xmm2, %xmm3
327 ; SSE41-NEXT: paddb %xmm2, %xmm3
328 ; SSE41-NEXT: paddb %xmm1, %xmm1
329 ; SSE41-NEXT: movdqa %xmm1, %xmm0
330 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
331 ; SSE41-NEXT: movdqa %xmm2, %xmm0
332 ; SSE41-NEXT: retq
333 ;
334 ; AVX-LABEL: var_shift_v16i8:
335 ; AVX: # %bb.0:
336 ; AVX-NEXT: vpsllw $5, %xmm1, %xmm1
337 ; AVX-NEXT: vpsllw $4, %xmm0, %xmm2
338 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
339 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
340 ; AVX-NEXT: vpsllw $2, %xmm0, %xmm2
341 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
342 ; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1
343 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
344 ; AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm2
345 ; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1
346 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
347 ; AVX-NEXT: retq
348 ;
349 ; XOP-LABEL: var_shift_v16i8:
350 ; XOP: # %bb.0:
351 ; XOP-NEXT: vpshlb %xmm1, %xmm0, %xmm0
352 ; XOP-NEXT: retq
353 ;
354 ; AVX512DQ-LABEL: var_shift_v16i8:
355 ; AVX512DQ: # %bb.0:
356 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
357 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
358 ; AVX512DQ-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
359 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
360 ; AVX512DQ-NEXT: vzeroupper
361 ; AVX512DQ-NEXT: retq
362 ;
363 ; AVX512BW-LABEL: var_shift_v16i8:
364 ; AVX512BW: # %bb.0:
365 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
366 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
367 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
368 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
369 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
370 ; AVX512BW-NEXT: vzeroupper
371 ; AVX512BW-NEXT: retq
372 ;
373 ; AVX512DQVL-LABEL: var_shift_v16i8:
374 ; AVX512DQVL: # %bb.0:
375 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
376 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
377 ; AVX512DQVL-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
378 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
379 ; AVX512DQVL-NEXT: vzeroupper
380 ; AVX512DQVL-NEXT: retq
381 ;
382 ; AVX512BWVL-LABEL: var_shift_v16i8:
383 ; AVX512BWVL: # %bb.0:
384 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
385 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
386 ; AVX512BWVL-NEXT: vpsllvw %ymm1, %ymm0, %ymm0
387 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
388 ; AVX512BWVL-NEXT: vzeroupper
389 ; AVX512BWVL-NEXT: retq
390 ;
391 ; X86-SSE-LABEL: var_shift_v16i8:
392 ; X86-SSE: # %bb.0:
393 ; X86-SSE-NEXT: psllw $5, %xmm1
394 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
395 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
396 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
397 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
398 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
399 ; X86-SSE-NEXT: psllw $4, %xmm0
400 ; X86-SSE-NEXT: pand %xmm3, %xmm0
401 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
402 ; X86-SSE-NEXT: por %xmm4, %xmm0
403 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
404 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
405 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
406 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
407 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
408 ; X86-SSE-NEXT: psllw $2, %xmm0
409 ; X86-SSE-NEXT: pand %xmm3, %xmm0
410 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
411 ; X86-SSE-NEXT: por %xmm4, %xmm0
412 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
413 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
414 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
415 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
416 ; X86-SSE-NEXT: paddb %xmm0, %xmm0
417 ; X86-SSE-NEXT: pand %xmm2, %xmm0
418 ; X86-SSE-NEXT: por %xmm1, %xmm0
419 ; X86-SSE-NEXT: retl
420 %shift = shl <16 x i8> %a, %b
421 ret <16 x i8> %shift
422 }
424 ;
425 ; Uniform Variable Shifts
426 ;
428 define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
429 ; SSE-LABEL: splatvar_shift_v2i64:
430 ; SSE: # %bb.0:
431 ; SSE-NEXT: psllq %xmm1, %xmm0
432 ; SSE-NEXT: retq
433 ;
434 ; AVX-LABEL: splatvar_shift_v2i64:
435 ; AVX: # %bb.0:
436 ; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
437 ; AVX-NEXT: retq
438 ;
439 ; XOP-LABEL: splatvar_shift_v2i64:
440 ; XOP: # %bb.0:
441 ; XOP-NEXT: vpsllq %xmm1, %xmm0, %xmm0
442 ; XOP-NEXT: retq
443 ;
444 ; AVX512-LABEL: splatvar_shift_v2i64:
445 ; AVX512: # %bb.0:
446 ; AVX512-NEXT: vpsllq %xmm1, %xmm0, %xmm0
447 ; AVX512-NEXT: retq
448 ;
449 ; AVX512VL-LABEL: splatvar_shift_v2i64:
450 ; AVX512VL: # %bb.0:
451 ; AVX512VL-NEXT: vpsllq %xmm1, %xmm0, %xmm0
452 ; AVX512VL-NEXT: retq
453 ;
454 ; X86-SSE-LABEL: splatvar_shift_v2i64:
455 ; X86-SSE: # %bb.0:
456 ; X86-SSE-NEXT: psllq %xmm1, %xmm0
457 ; X86-SSE-NEXT: retl
458 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
459 %shift = shl <2 x i64> %a, %splat
460 ret <2 x i64> %shift
461 }
463 define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
464 ; SSE2-LABEL: splatvar_shift_v4i32:
465 ; SSE2: # %bb.0:
466 ; SSE2-NEXT: xorps %xmm2, %xmm2
467 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
468 ; SSE2-NEXT: pslld %xmm2, %xmm0
469 ; SSE2-NEXT: retq
470 ;
471 ; SSE41-LABEL: splatvar_shift_v4i32:
472 ; SSE41: # %bb.0:
473 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
474 ; SSE41-NEXT: pslld %xmm1, %xmm0
475 ; SSE41-NEXT: retq
476 ;
477 ; AVX-LABEL: splatvar_shift_v4i32:
478 ; AVX: # %bb.0:
479 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
480 ; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
481 ; AVX-NEXT: retq
482 ;
483 ; XOP-LABEL: splatvar_shift_v4i32:
484 ; XOP: # %bb.0:
485 ; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
486 ; XOP-NEXT: vpslld %xmm1, %xmm0, %xmm0
487 ; XOP-NEXT: retq
488 ;
489 ; AVX512-LABEL: splatvar_shift_v4i32:
490 ; AVX512: # %bb.0:
491 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
492 ; AVX512-NEXT: vpslld %xmm1, %xmm0, %xmm0
493 ; AVX512-NEXT: retq
494 ;
495 ; AVX512VL-LABEL: splatvar_shift_v4i32:
496 ; AVX512VL: # %bb.0:
497 ; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
498 ; AVX512VL-NEXT: vpslld %xmm1, %xmm0, %xmm0
499 ; AVX512VL-NEXT: retq
500 ;
501 ; X86-SSE-LABEL: splatvar_shift_v4i32:
502 ; X86-SSE: # %bb.0:
503 ; X86-SSE-NEXT: xorps %xmm2, %xmm2
504 ; X86-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
505 ; X86-SSE-NEXT: pslld %xmm2, %xmm0
506 ; X86-SSE-NEXT: retl
507 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
508 %shift = shl <4 x i32> %a, %splat
509 ret <4 x i32> %shift
510 }
512 define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
513 ; SSE2-LABEL: splatvar_shift_v8i16:
514 ; SSE2: # %bb.0:
515 ; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
516 ; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
517 ; SSE2-NEXT: psllw %xmm1, %xmm0
518 ; SSE2-NEXT: retq
519 ;
520 ; SSE41-LABEL: splatvar_shift_v8i16:
521 ; SSE41: # %bb.0:
522 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
523 ; SSE41-NEXT: psllw %xmm1, %xmm0
524 ; SSE41-NEXT: retq
525 ;
526 ; AVX-LABEL: splatvar_shift_v8i16:
527 ; AVX: # %bb.0:
528 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
529 ; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
530 ; AVX-NEXT: retq
531 ;
532 ; XOP-LABEL: splatvar_shift_v8i16:
533 ; XOP: # %bb.0:
534 ; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
535 ; XOP-NEXT: vpsllw %xmm1, %xmm0, %xmm0
536 ; XOP-NEXT: retq
537 ;
538 ; AVX512-LABEL: splatvar_shift_v8i16:
539 ; AVX512: # %bb.0:
540 ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
541 ; AVX512-NEXT: vpsllw %xmm1, %xmm0, %xmm0
542 ; AVX512-NEXT: retq
543 ;
544 ; AVX512VL-LABEL: splatvar_shift_v8i16:
545 ; AVX512VL: # %bb.0:
546 ; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
547 ; AVX512VL-NEXT: vpsllw %xmm1, %xmm0, %xmm0
548 ; AVX512VL-NEXT: retq
549 ;
550 ; X86-SSE-LABEL: splatvar_shift_v8i16:
551 ; X86-SSE: # %bb.0:
552 ; X86-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
553 ; X86-SSE-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
554 ; X86-SSE-NEXT: psllw %xmm1, %xmm0
555 ; X86-SSE-NEXT: retl
556 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer
557 %shift = shl <8 x i16> %a, %splat
558 ret <8 x i16> %shift
559 }
561 define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
562 ; SSE2-LABEL: splatvar_shift_v16i8:
563 ; SSE2: # %bb.0:
564 ; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
565 ; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
566 ; SSE2-NEXT: psllw %xmm1, %xmm0
567 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
568 ; SSE2-NEXT: psllw %xmm1, %xmm2
569 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
570 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,0,0,4,5,6,7]
571 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
572 ; SSE2-NEXT: pand %xmm1, %xmm0
573 ; SSE2-NEXT: retq
574 ;
575 ; SSE41-LABEL: splatvar_shift_v16i8:
576 ; SSE41: # %bb.0:
577 ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
578 ; SSE41-NEXT: psllw %xmm1, %xmm0
579 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
580 ; SSE41-NEXT: psllw %xmm1, %xmm2
581 ; SSE41-NEXT: pxor %xmm1, %xmm1
582 ; SSE41-NEXT: pshufb %xmm1, %xmm2
583 ; SSE41-NEXT: pand %xmm2, %xmm0
584 ; SSE41-NEXT: retq
585 ;
586 ; AVX1-LABEL: splatvar_shift_v16i8:
587 ; AVX1: # %bb.0:
588 ; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
589 ; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0
590 ; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
591 ; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm1
592 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
593 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
594 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
595 ; AVX1-NEXT: retq
596 ;
597 ; AVX2-LABEL: splatvar_shift_v16i8:
598 ; AVX2: # %bb.0:
599 ; AVX2-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
600 ; AVX2-NEXT: vpsllw %xmm1, %xmm0, %xmm0
601 ; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
602 ; AVX2-NEXT: vpsllw %xmm1, %xmm2, %xmm1
603 ; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
604 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
605 ; AVX2-NEXT: retq
606 ;
607 ; XOPAVX1-LABEL: splatvar_shift_v16i8:
608 ; XOPAVX1: # %bb.0:
609 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
610 ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
611 ; XOPAVX1-NEXT: vpshlb %xmm1, %xmm0, %xmm0
612 ; XOPAVX1-NEXT: retq
613 ;
614 ; XOPAVX2-LABEL: splatvar_shift_v16i8:
615 ; XOPAVX2: # %bb.0:
616 ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
617 ; XOPAVX2-NEXT: vpshlb %xmm1, %xmm0, %xmm0
618 ; XOPAVX2-NEXT: retq
619 ;
620 ; AVX512DQ-LABEL: splatvar_shift_v16i8:
621 ; AVX512DQ: # %bb.0:
622 ; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
623 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
624 ; AVX512DQ-NEXT: vpslld %xmm1, %zmm0, %zmm0
625 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
626 ; AVX512DQ-NEXT: vzeroupper
627 ; AVX512DQ-NEXT: retq
628 ;
629 ; AVX512BW-LABEL: splatvar_shift_v16i8:
630 ; AVX512BW: # %bb.0:
631 ; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
632 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
633 ; AVX512BW-NEXT: vpsllw %xmm1, %ymm0, %ymm0
634 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
635 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
636 ; AVX512BW-NEXT: vzeroupper
637 ; AVX512BW-NEXT: retq
638 ;
639 ; AVX512DQVL-LABEL: splatvar_shift_v16i8:
640 ; AVX512DQVL: # %bb.0:
641 ; AVX512DQVL-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
642 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
643 ; AVX512DQVL-NEXT: vpslld %xmm1, %zmm0, %zmm0
644 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
645 ; AVX512DQVL-NEXT: vzeroupper
646 ; AVX512DQVL-NEXT: retq
647 ;
648 ; AVX512BWVL-LABEL: splatvar_shift_v16i8:
649 ; AVX512BWVL: # %bb.0:
650 ; AVX512BWVL-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
651 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
652 ; AVX512BWVL-NEXT: vpsllw %xmm1, %ymm0, %ymm0
653 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
654 ; AVX512BWVL-NEXT: vzeroupper
655 ; AVX512BWVL-NEXT: retq
656 ;
657 ; X86-SSE-LABEL: splatvar_shift_v16i8:
658 ; X86-SSE: # %bb.0:
659 ; X86-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
660 ; X86-SSE-NEXT: psrldq {{.*#+}} xmm1 = xmm1[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
661 ; X86-SSE-NEXT: psllw %xmm1, %xmm0
662 ; X86-SSE-NEXT: pcmpeqd %xmm2, %xmm2
663 ; X86-SSE-NEXT: psllw %xmm1, %xmm2
664 ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
665 ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,0,0,4,5,6,7]
666 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
667 ; X86-SSE-NEXT: pand %xmm1, %xmm0
668 ; X86-SSE-NEXT: retl
669 %splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
670 %shift = shl <16 x i8> %a, %splat
671 ret <16 x i8> %shift
672 }
674 ;
675 ; Uniform Variable Modulo Shifts
676 ;
678 define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
679 ; SSE-LABEL: splatvar_modulo_shift_v2i64:
680 ; SSE: # %bb.0:
681 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
682 ; SSE-NEXT: psllq %xmm1, %xmm0
683 ; SSE-NEXT: retq
684 ;
685 ; AVX-LABEL: splatvar_modulo_shift_v2i64:
686 ; AVX: # %bb.0:
687 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
688 ; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
689 ; AVX-NEXT: retq
690 ;
691 ; XOP-LABEL: splatvar_modulo_shift_v2i64:
692 ; XOP: # %bb.0:
693 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
694 ; XOP-NEXT: vpsllq %xmm1, %xmm0, %xmm0
695 ; XOP-NEXT: retq
696 ;
697 ; AVX512-LABEL: splatvar_modulo_shift_v2i64:
698 ; AVX512: # %bb.0:
699 ; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
700 ; AVX512-NEXT: vpsllq %xmm1, %xmm0, %xmm0
701 ; AVX512-NEXT: retq
702 ;
703 ; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
704 ; AVX512VL: # %bb.0:
705 ; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
706 ; AVX512VL-NEXT: vpsllq %xmm1, %xmm0, %xmm0
707 ; AVX512VL-NEXT: retq
708 ;
709 ; X86-SSE-LABEL: splatvar_modulo_shift_v2i64:
710 ; X86-SSE: # %bb.0:
711 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
712 ; X86-SSE-NEXT: psllq %xmm1, %xmm0
713 ; X86-SSE-NEXT: retl
714 %mod = and <2 x i64> %b, <i64 63, i64 63>
715 %splat = shufflevector <2 x i64> %mod, <2 x i64> undef, <2 x i32> zeroinitializer
716 %shift = shl <2 x i64> %a, %splat
717 ret <2 x i64> %shift
718 }
720 define <4 x i32> @splatvar_modulo_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
721 ; SSE-LABEL: splatvar_modulo_shift_v4i32:
722 ; SSE: # %bb.0:
723 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
724 ; SSE-NEXT: pslld %xmm1, %xmm0
725 ; SSE-NEXT: retq
726 ;
727 ; AVX-LABEL: splatvar_modulo_shift_v4i32:
728 ; AVX: # %bb.0:
729 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
730 ; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
731 ; AVX-NEXT: retq
732 ;
733 ; XOP-LABEL: splatvar_modulo_shift_v4i32:
734 ; XOP: # %bb.0:
735 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
736 ; XOP-NEXT: vpslld %xmm1, %xmm0, %xmm0
737 ; XOP-NEXT: retq
738 ;
739 ; AVX512-LABEL: splatvar_modulo_shift_v4i32:
740 ; AVX512: # %bb.0:
741 ; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
742 ; AVX512-NEXT: vpslld %xmm1, %xmm0, %xmm0
743 ; AVX512-NEXT: retq
744 ;
745 ; AVX512VL-LABEL: splatvar_modulo_shift_v4i32:
746 ; AVX512VL: # %bb.0:
747 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
748 ; AVX512VL-NEXT: vpslld %xmm1, %xmm0, %xmm0
749 ; AVX512VL-NEXT: retq
750 ;
751 ; X86-SSE-LABEL: splatvar_modulo_shift_v4i32:
752 ; X86-SSE: # %bb.0:
753 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
754 ; X86-SSE-NEXT: pslld %xmm1, %xmm0
755 ; X86-SSE-NEXT: retl
756 %mod = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
757 %splat = shufflevector <4 x i32> %mod, <4 x i32> undef, <4 x i32> zeroinitializer
758 %shift = shl <4 x i32> %a, %splat
759 ret <4 x i32> %shift
760 }
762 define <8 x i16> @splatvar_modulo_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
763 ; SSE-LABEL: splatvar_modulo_shift_v8i16:
764 ; SSE: # %bb.0:
765 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
766 ; SSE-NEXT: psllw %xmm1, %xmm0
767 ; SSE-NEXT: retq
768 ;
769 ; AVX-LABEL: splatvar_modulo_shift_v8i16:
770 ; AVX: # %bb.0:
771 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
772 ; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
773 ; AVX-NEXT: retq
774 ;
775 ; XOP-LABEL: splatvar_modulo_shift_v8i16:
776 ; XOP: # %bb.0:
777 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
778 ; XOP-NEXT: vpsllw %xmm1, %xmm0, %xmm0
779 ; XOP-NEXT: retq
780 ;
781 ; AVX512-LABEL: splatvar_modulo_shift_v8i16:
782 ; AVX512: # %bb.0:
783 ; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
784 ; AVX512-NEXT: vpsllw %xmm1, %xmm0, %xmm0
785 ; AVX512-NEXT: retq
786 ;
787 ; AVX512VL-LABEL: splatvar_modulo_shift_v8i16:
788 ; AVX512VL: # %bb.0:
789 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
790 ; AVX512VL-NEXT: vpsllw %xmm1, %xmm0, %xmm0
791 ; AVX512VL-NEXT: retq
792 ;
793 ; X86-SSE-LABEL: splatvar_modulo_shift_v8i16:
794 ; X86-SSE: # %bb.0:
795 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
796 ; X86-SSE-NEXT: psllw %xmm1, %xmm0
797 ; X86-SSE-NEXT: retl
798 %mod = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
799 %splat = shufflevector <8 x i16> %mod, <8 x i16> undef, <8 x i32> zeroinitializer
800 %shift = shl <8 x i16> %a, %splat
801 ret <8 x i16> %shift
802 }
804 define <16 x i8> @splatvar_modulo_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
805 ; SSE2-LABEL: splatvar_modulo_shift_v16i8:
806 ; SSE2: # %bb.0:
807 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
808 ; SSE2-NEXT: psllw %xmm1, %xmm0
809 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
810 ; SSE2-NEXT: psllw %xmm1, %xmm2
811 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
812 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,0,0,4,5,6,7]
813 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
814 ; SSE2-NEXT: pand %xmm1, %xmm0
815 ; SSE2-NEXT: retq
816 ;
817 ; SSE41-LABEL: splatvar_modulo_shift_v16i8:
818 ; SSE41: # %bb.0:
819 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
820 ; SSE41-NEXT: psllw %xmm1, %xmm0
821 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
822 ; SSE41-NEXT: psllw %xmm1, %xmm2
823 ; SSE41-NEXT: pxor %xmm1, %xmm1
824 ; SSE41-NEXT: pshufb %xmm1, %xmm2
825 ; SSE41-NEXT: pand %xmm2, %xmm0
826 ; SSE41-NEXT: retq
827 ;
828 ; AVX1-LABEL: splatvar_modulo_shift_v16i8:
829 ; AVX1: # %bb.0:
830 ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
831 ; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0
832 ; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
833 ; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm1
834 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
835 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
836 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
837 ; AVX1-NEXT: retq
838 ;
839 ; AVX2-LABEL: splatvar_modulo_shift_v16i8:
840 ; AVX2: # %bb.0:
841 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
842 ; AVX2-NEXT: vpsllw %xmm1, %xmm0, %xmm0
843 ; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
844 ; AVX2-NEXT: vpsllw %xmm1, %xmm2, %xmm1
845 ; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
846 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
847 ; AVX2-NEXT: retq
848 ;
849 ; XOPAVX1-LABEL: splatvar_modulo_shift_v16i8:
850 ; XOPAVX1: # %bb.0:
851 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
852 ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
853 ; XOPAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
854 ; XOPAVX1-NEXT: vpshlb %xmm1, %xmm0, %xmm0
855 ; XOPAVX1-NEXT: retq
856 ;
857 ; XOPAVX2-LABEL: splatvar_modulo_shift_v16i8:
858 ; XOPAVX2: # %bb.0:
859 ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
860 ; XOPAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
861 ; XOPAVX2-NEXT: vpshlb %xmm1, %xmm0, %xmm0
862 ; XOPAVX2-NEXT: retq
863 ;
864 ; AVX512DQ-LABEL: splatvar_modulo_shift_v16i8:
865 ; AVX512DQ: # %bb.0:
866 ; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
867 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
868 ; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
869 ; AVX512DQ-NEXT: vpslld %xmm1, %zmm0, %zmm0
870 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
871 ; AVX512DQ-NEXT: vzeroupper
872 ; AVX512DQ-NEXT: retq
873 ;
874 ; AVX512BW-LABEL: splatvar_modulo_shift_v16i8:
875 ; AVX512BW: # %bb.0:
876 ; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
877 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
878 ; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
879 ; AVX512BW-NEXT: vpsllw %xmm1, %ymm0, %ymm0
880 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
881 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
882 ; AVX512BW-NEXT: vzeroupper
883 ; AVX512BW-NEXT: retq
884 ;
885 ; AVX512DQVL-LABEL: splatvar_modulo_shift_v16i8:
886 ; AVX512DQVL: # %bb.0:
887 ; AVX512DQVL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
888 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
889 ; AVX512DQVL-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
890 ; AVX512DQVL-NEXT: vpslld %xmm1, %zmm0, %zmm0
891 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
892 ; AVX512DQVL-NEXT: vzeroupper
893 ; AVX512DQVL-NEXT: retq
894 ;
895 ; AVX512BWVL-LABEL: splatvar_modulo_shift_v16i8:
896 ; AVX512BWVL: # %bb.0:
897 ; AVX512BWVL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
898 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
899 ; AVX512BWVL-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
900 ; AVX512BWVL-NEXT: vpsllw %xmm1, %ymm0, %ymm0
901 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
902 ; AVX512BWVL-NEXT: vzeroupper
903 ; AVX512BWVL-NEXT: retq
904 ;
905 ; X86-SSE-LABEL: splatvar_modulo_shift_v16i8:
906 ; X86-SSE: # %bb.0:
907 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
908 ; X86-SSE-NEXT: psllw %xmm1, %xmm0
909 ; X86-SSE-NEXT: pcmpeqd %xmm2, %xmm2
910 ; X86-SSE-NEXT: psllw %xmm1, %xmm2
911 ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
912 ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,0,0,4,5,6,7]
913 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
914 ; X86-SSE-NEXT: pand %xmm1, %xmm0
915 ; X86-SSE-NEXT: retl
916 %mod = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
917 %splat = shufflevector <16 x i8> %mod, <16 x i8> undef, <16 x i32> zeroinitializer
918 %shift = shl <16 x i8> %a, %splat
919 ret <16 x i8> %shift
920 }
922 ;
923 ; Constant Shifts
924 ;
926 define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
927 ; SSE2-LABEL: constant_shift_v2i64:
928 ; SSE2: # %bb.0:
929 ; SSE2-NEXT: movdqa %xmm0, %xmm1
930 ; SSE2-NEXT: paddq %xmm0, %xmm1
931 ; SSE2-NEXT: psllq $7, %xmm0
932 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
933 ; SSE2-NEXT: retq
934 ;
935 ; SSE41-LABEL: constant_shift_v2i64:
936 ; SSE41: # %bb.0:
937 ; SSE41-NEXT: movdqa %xmm0, %xmm1
938 ; SSE41-NEXT: psllq $7, %xmm1
939 ; SSE41-NEXT: paddq %xmm0, %xmm0
940 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
941 ; SSE41-NEXT: retq
942 ;
943 ; AVX1-LABEL: constant_shift_v2i64:
944 ; AVX1: # %bb.0:
945 ; AVX1-NEXT: vpsllq $7, %xmm0, %xmm1
946 ; AVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0
947 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
948 ; AVX1-NEXT: retq
949 ;
950 ; AVX2-LABEL: constant_shift_v2i64:
951 ; AVX2: # %bb.0:
952 ; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
953 ; AVX2-NEXT: retq
954 ;
955 ; XOPAVX1-LABEL: constant_shift_v2i64:
956 ; XOPAVX1: # %bb.0:
957 ; XOPAVX1-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
958 ; XOPAVX1-NEXT: retq
959 ;
960 ; XOPAVX2-LABEL: constant_shift_v2i64:
961 ; XOPAVX2: # %bb.0:
962 ; XOPAVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
963 ; XOPAVX2-NEXT: retq
964 ;
965 ; AVX512-LABEL: constant_shift_v2i64:
966 ; AVX512: # %bb.0:
967 ; AVX512-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
968 ; AVX512-NEXT: retq
969 ;
970 ; AVX512VL-LABEL: constant_shift_v2i64:
971 ; AVX512VL: # %bb.0:
972 ; AVX512VL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
973 ; AVX512VL-NEXT: retq
974 ;
975 ; X86-SSE-LABEL: constant_shift_v2i64:
976 ; X86-SSE: # %bb.0:
977 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
978 ; X86-SSE-NEXT: paddq %xmm0, %xmm1
979 ; X86-SSE-NEXT: psllq $7, %xmm0
980 ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
981 ; X86-SSE-NEXT: retl
982 %shift = shl <2 x i64> %a, <i64 1, i64 7>
983 ret <2 x i64> %shift
984 }
986 define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
987 ; SSE2-LABEL: constant_shift_v4i32:
988 ; SSE2: # %bb.0:
989 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
990 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
991 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
992 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
993 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
994 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
995 ; SSE2-NEXT: retq
996 ;
997 ; SSE41-LABEL: constant_shift_v4i32:
998 ; SSE41: # %bb.0:
999 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1000 ; SSE41-NEXT: retq
1001 ;
1002 ; AVX1-LABEL: constant_shift_v4i32:
1003 ; AVX1: # %bb.0:
1004 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1005 ; AVX1-NEXT: retq
1006 ;
1007 ; AVX2-LABEL: constant_shift_v4i32:
1008 ; AVX2: # %bb.0:
1009 ; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1010 ; AVX2-NEXT: retq
1011 ;
1012 ; XOPAVX1-LABEL: constant_shift_v4i32:
1013 ; XOPAVX1: # %bb.0:
1014 ; XOPAVX1-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1015 ; XOPAVX1-NEXT: retq
1016 ;
1017 ; XOPAVX2-LABEL: constant_shift_v4i32:
1018 ; XOPAVX2: # %bb.0:
1019 ; XOPAVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1020 ; XOPAVX2-NEXT: retq
1021 ;
1022 ; AVX512-LABEL: constant_shift_v4i32:
1023 ; AVX512: # %bb.0:
1024 ; AVX512-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1025 ; AVX512-NEXT: retq
1026 ;
1027 ; AVX512VL-LABEL: constant_shift_v4i32:
1028 ; AVX512VL: # %bb.0:
1029 ; AVX512VL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1030 ; AVX512VL-NEXT: retq
1031 ;
1032 ; X86-SSE-LABEL: constant_shift_v4i32:
1033 ; X86-SSE: # %bb.0:
1034 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
1035 ; X86-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
1036 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1037 ; X86-SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
1038 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1039 ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1040 ; X86-SSE-NEXT: retl
1041 %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
1042 ret <4 x i32> %shift
1043 }
1045 define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
1046 ; SSE-LABEL: constant_shift_v8i16:
1047 ; SSE: # %bb.0:
1048 ; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1,2,4,8,16,32,64,128]
1049 ; SSE-NEXT: retq
1050 ;
1051 ; AVX-LABEL: constant_shift_v8i16:
1052 ; AVX: # %bb.0:
1053 ; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,4,8,16,32,64,128]
1054 ; AVX-NEXT: retq
1055 ;
1056 ; XOP-LABEL: constant_shift_v8i16:
1057 ; XOP: # %bb.0:
1058 ; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1059 ; XOP-NEXT: retq
1060 ;
1061 ; AVX512DQ-LABEL: constant_shift_v8i16:
1062 ; AVX512DQ: # %bb.0:
1063 ; AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,4,8,16,32,64,128]
1064 ; AVX512DQ-NEXT: retq
1065 ;
1066 ; AVX512BW-LABEL: constant_shift_v8i16:
1067 ; AVX512BW: # %bb.0:
1068 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
1069 ; AVX512BW-NEXT: vpmovsxbw {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7]
1070 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
1071 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
1072 ; AVX512BW-NEXT: vzeroupper
1073 ; AVX512BW-NEXT: retq
1074 ;
1075 ; AVX512DQVL-LABEL: constant_shift_v8i16:
1076 ; AVX512DQVL: # %bb.0:
1077 ; AVX512DQVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,4,8,16,32,64,128]
1078 ; AVX512DQVL-NEXT: retq
1079 ;
1080 ; AVX512BWVL-LABEL: constant_shift_v8i16:
1081 ; AVX512BWVL: # %bb.0:
1082 ; AVX512BWVL-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1083 ; AVX512BWVL-NEXT: retq
1084 ;
1085 ; X86-SSE-LABEL: constant_shift_v8i16:
1086 ; X86-SSE: # %bb.0:
1087 ; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [1,2,4,8,16,32,64,128]
1088 ; X86-SSE-NEXT: retl
1089 %shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
1090 ret <8 x i16> %shift
1091 }
1093 define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
1094 ; SSE2-LABEL: constant_shift_v16i8:
1095 ; SSE2: # %bb.0:
1096 ; SSE2-NEXT: movdqa %xmm0, %xmm1
1097 ; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
1098 ; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [128,64,32,16,8,4,2,1]
1099 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
1100 ; SSE2-NEXT: pand %xmm2, %xmm1
1101 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1102 ; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1,2,4,8,16,32,64,128]
1103 ; SSE2-NEXT: pand %xmm2, %xmm0
1104 ; SSE2-NEXT: packuswb %xmm1, %xmm0
1105 ; SSE2-NEXT: retq
1106 ;
1107 ; SSE41-LABEL: constant_shift_v16i8:
1108 ; SSE41: # %bb.0:
1109 ; SSE41-NEXT: movdqa %xmm0, %xmm1
1110 ; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
1111 ; SSE41-NEXT: psllw $8, %xmm1
1112 ; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
1113 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1114 ; SSE41-NEXT: por %xmm1, %xmm0
1115 ; SSE41-NEXT: retq
1116 ;
1117 ; AVX1-LABEL: constant_shift_v16i8:
1118 ; AVX1: # %bb.0:
1119 ; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
1120 ; AVX1-NEXT: vpsllw $8, %xmm1, %xmm1
1121 ; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
1122 ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1123 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
1124 ; AVX1-NEXT: retq
1125 ;
1126 ; AVX2-LABEL: constant_shift_v16i8:
1127 ; AVX2: # %bb.0:
1128 ; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1129 ; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1]
1130 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1131 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1132 ; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1133 ; AVX2-NEXT: vzeroupper
1134 ; AVX2-NEXT: retq
1135 ;
1136 ; XOP-LABEL: constant_shift_v16i8:
1137 ; XOP: # %bb.0:
1138 ; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1139 ; XOP-NEXT: retq
1140 ;
1141 ; AVX512DQ-LABEL: constant_shift_v16i8:
1142 ; AVX512DQ: # %bb.0:
1143 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
1144 ; AVX512DQ-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
1145 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
1146 ; AVX512DQ-NEXT: vzeroupper
1147 ; AVX512DQ-NEXT: retq
1148 ;
1149 ; AVX512BW-LABEL: constant_shift_v16i8:
1150 ; AVX512BW: # %bb.0:
1151 ; AVX512BW-NEXT: vpmovsxbw {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
1152 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1153 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
1154 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
1155 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
1156 ; AVX512BW-NEXT: vzeroupper
1157 ; AVX512BW-NEXT: retq
1158 ;
1159 ; AVX512DQVL-LABEL: constant_shift_v16i8:
1160 ; AVX512DQVL: # %bb.0:
1161 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
1162 ; AVX512DQVL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
1163 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
1164 ; AVX512DQVL-NEXT: vzeroupper
1165 ; AVX512DQVL-NEXT: retq
1166 ;
1167 ; AVX512BWVL-LABEL: constant_shift_v16i8:
1168 ; AVX512BWVL: # %bb.0:
1169 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1170 ; AVX512BWVL-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1171 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
1172 ; AVX512BWVL-NEXT: vzeroupper
1173 ; AVX512BWVL-NEXT: retq
1174 ;
1175 ; X86-SSE-LABEL: constant_shift_v16i8:
1176 ; X86-SSE: # %bb.0:
1177 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
1178 ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
1179 ; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 # [128,64,32,16,8,4,2,1]
1180 ; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
1181 ; X86-SSE-NEXT: pand %xmm2, %xmm1
1182 ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1183 ; X86-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [1,2,4,8,16,32,64,128]
1184 ; X86-SSE-NEXT: pand %xmm2, %xmm0
1185 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
1186 ; X86-SSE-NEXT: retl
1187 %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
1188 ret <16 x i8> %shift
1189 }
1191 ;
1192 ; Uniform Constant Shifts
1193 ;
1195 define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
1196 ; SSE-LABEL: splatconstant_shift_v2i64:
1197 ; SSE: # %bb.0:
1198 ; SSE-NEXT: psllq $7, %xmm0
1199 ; SSE-NEXT: retq
1200 ;
1201 ; AVX-LABEL: splatconstant_shift_v2i64:
1202 ; AVX: # %bb.0:
1203 ; AVX-NEXT: vpsllq $7, %xmm0, %xmm0
1204 ; AVX-NEXT: retq
1205 ;
1206 ; XOP-LABEL: splatconstant_shift_v2i64:
1207 ; XOP: # %bb.0:
1208 ; XOP-NEXT: vpsllq $7, %xmm0, %xmm0
1209 ; XOP-NEXT: retq
1210 ;
1211 ; AVX512-LABEL: splatconstant_shift_v2i64:
1212 ; AVX512: # %bb.0:
1213 ; AVX512-NEXT: vpsllq $7, %xmm0, %xmm0
1214 ; AVX512-NEXT: retq
1215 ;
1216 ; AVX512VL-LABEL: splatconstant_shift_v2i64:
1217 ; AVX512VL: # %bb.0:
1218 ; AVX512VL-NEXT: vpsllq $7, %xmm0, %xmm0
1219 ; AVX512VL-NEXT: retq
1220 ;
1221 ; X86-SSE-LABEL: splatconstant_shift_v2i64:
1222 ; X86-SSE: # %bb.0:
1223 ; X86-SSE-NEXT: psllq $7, %xmm0
1224 ; X86-SSE-NEXT: retl
1225 %shift = shl <2 x i64> %a, <i64 7, i64 7>
1226 ret <2 x i64> %shift
1227 }
1229 define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
1230 ; SSE-LABEL: splatconstant_shift_v4i32:
1231 ; SSE: # %bb.0:
1232 ; SSE-NEXT: pslld $5, %xmm0
1233 ; SSE-NEXT: retq
1234 ;
1235 ; AVX-LABEL: splatconstant_shift_v4i32:
1236 ; AVX: # %bb.0:
1237 ; AVX-NEXT: vpslld $5, %xmm0, %xmm0
1238 ; AVX-NEXT: retq
1239 ;
1240 ; XOP-LABEL: splatconstant_shift_v4i32:
1241 ; XOP: # %bb.0:
1242 ; XOP-NEXT: vpslld $5, %xmm0, %xmm0
1243 ; XOP-NEXT: retq
1244 ;
1245 ; AVX512-LABEL: splatconstant_shift_v4i32:
1246 ; AVX512: # %bb.0:
1247 ; AVX512-NEXT: vpslld $5, %xmm0, %xmm0
1248 ; AVX512-NEXT: retq
1249 ;
1250 ; AVX512VL-LABEL: splatconstant_shift_v4i32:
1251 ; AVX512VL: # %bb.0:
1252 ; AVX512VL-NEXT: vpslld $5, %xmm0, %xmm0
1253 ; AVX512VL-NEXT: retq
1254 ;
1255 ; X86-SSE-LABEL: splatconstant_shift_v4i32:
1256 ; X86-SSE: # %bb.0:
1257 ; X86-SSE-NEXT: pslld $5, %xmm0
1258 ; X86-SSE-NEXT: retl
1259 %shift = shl <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
1260 ret <4 x i32> %shift
1261 }
1263 define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
1264 ; SSE-LABEL: splatconstant_shift_v8i16:
1265 ; SSE: # %bb.0:
1266 ; SSE-NEXT: psllw $3, %xmm0
1267 ; SSE-NEXT: retq
1268 ;
1269 ; AVX-LABEL: splatconstant_shift_v8i16:
1270 ; AVX: # %bb.0:
1271 ; AVX-NEXT: vpsllw $3, %xmm0, %xmm0
1272 ; AVX-NEXT: retq
1273 ;
1274 ; XOP-LABEL: splatconstant_shift_v8i16:
1275 ; XOP: # %bb.0:
1276 ; XOP-NEXT: vpsllw $3, %xmm0, %xmm0
1277 ; XOP-NEXT: retq
1278 ;
1279 ; AVX512-LABEL: splatconstant_shift_v8i16:
1280 ; AVX512: # %bb.0:
1281 ; AVX512-NEXT: vpsllw $3, %xmm0, %xmm0
1282 ; AVX512-NEXT: retq
1283 ;
1284 ; AVX512VL-LABEL: splatconstant_shift_v8i16:
1285 ; AVX512VL: # %bb.0:
1286 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
1287 ; AVX512VL-NEXT: retq
1288 ;
1289 ; X86-SSE-LABEL: splatconstant_shift_v8i16:
1290 ; X86-SSE: # %bb.0:
1291 ; X86-SSE-NEXT: psllw $3, %xmm0
1292 ; X86-SSE-NEXT: retl
1293 %shift = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
1294 ret <8 x i16> %shift
1295 }
1297 define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
1298 ; SSE-LABEL: splatconstant_shift_v16i8:
1299 ; SSE: # %bb.0:
1300 ; SSE-NEXT: psllw $3, %xmm0
1301 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
1302 ; SSE-NEXT: retq
1303 ;
1304 ; AVX-LABEL: splatconstant_shift_v16i8:
1305 ; AVX: # %bb.0:
1306 ; AVX-NEXT: vpsllw $3, %xmm0, %xmm0
1307 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1308 ; AVX-NEXT: retq
1309 ;
1310 ; XOP-LABEL: splatconstant_shift_v16i8:
1311 ; XOP: # %bb.0:
1312 ; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1313 ; XOP-NEXT: retq
1314 ;
1315 ; AVX512-LABEL: splatconstant_shift_v16i8:
1316 ; AVX512: # %bb.0:
1317 ; AVX512-NEXT: vpsllw $3, %xmm0, %xmm0
1318 ; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1319 ; AVX512-NEXT: retq
1320 ;
1321 ; AVX512VL-LABEL: splatconstant_shift_v16i8:
1322 ; AVX512VL: # %bb.0:
1323 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
1324 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
1325 ; AVX512VL-NEXT: retq
1326 ;
1327 ; X86-SSE-LABEL: splatconstant_shift_v16i8:
1328 ; X86-SSE: # %bb.0:
1329 ; X86-SSE-NEXT: psllw $3, %xmm0
1330 ; X86-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
1331 ; X86-SSE-NEXT: retl
1332 %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
1333 ret <16 x i8> %shift
1334 }