[RemoveDIs][DebugInfo] Update SROA to handle DPVAssigns (#78475)
[llvm-project.git] / llvm / test / MC / ELF / relax-arith.s
blobc9bd2afcf6bd5ebdbf7d3e566048224d22a867aa
1 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
3 // Test that we correctly relax these instructions into versions that use
4 // 16 or 32 bit immediate values.
6 bar:
7 // CHECK: Disassembly of section imul:
8 // CHECK-EMPTY:
9 // CHECK-NEXT: <imul>:
10 // CHECK-NEXT: 0: 66 69 db 00 00 imulw $0, %bx, %bx
11 // CHECK-NEXT: 5: 66 69 1c 25 00 00 00 00 00 00 imulw $0, 0, %bx
12 // CHECK-NEXT: f: 69 db 00 00 00 00 imull $0, %ebx, %ebx
13 // CHECK-NEXT: 15: 69 1c 25 00 00 00 00 00 00 00 00 imull $0, 0, %ebx
14 // CHECK-NEXT: 20: 48 69 db 00 00 00 00 imulq $0, %rbx, %rbx
15 // CHECK-NEXT: 27: 48 69 1c 25 00 00 00 00 00 00 00 00 imulq $0, 0, %rbx
16 .section imul,"x"
17 imul $foo, %bx, %bx
18 imul $foo, bar, %bx
19 imul $foo, %ebx, %ebx
20 imul $foo, bar, %ebx
21 imul $foo, %rbx, %rbx
22 imul $foo, bar, %rbx
24 // CHECK: Disassembly of section and:
25 // CHECK-EMPTY:
26 // CHECK-NEXT: <and>:
27 // CHECK-NEXT: 0: 66 81 e3 00 00 andw $0, %bx
28 // CHECK-NEXT: 5: 66 81 24 25 00 00 00 00 00 00 andw $0, 0
29 // CHECK-NEXT: f: 81 e3 00 00 00 00 andl $0, %ebx
30 // CHECK-NEXT: 15: 81 24 25 00 00 00 00 00 00 00 00 andl $0, 0
31 // CHECK-NEXT: 20: 48 81 e3 00 00 00 00 andq $0, %rbx
32 // CHECK-NEXT: 27: 48 81 24 25 00 00 00 00 00 00 00 00 andq $0, 0
33 .section and,"x"
34 and $foo, %bx
35 andw $foo, bar
36 and $foo, %ebx
37 andl $foo, bar
38 and $foo, %rbx
39 andq $foo, bar
41 // CHECK: <or>:
42 // CHECK-NEXT: 0: 66 81 cb 00 00 orw $0, %bx
43 // CHECK-NEXT: 5: 66 81 0c 25 00 00 00 00 00 00 orw $0, 0
44 // CHECK-NEXT: f: 81 cb 00 00 00 00 orl $0, %ebx
45 // CHECK-NEXT: 15: 81 0c 25 00 00 00 00 00 00 00 00 orl $0, 0
46 // CHECK-NEXT: 20: 48 81 cb 00 00 00 00 orq $0, %rbx
47 // CHECK-NEXT: 27: 48 81 0c 25 00 00 00 00 00 00 00 00 orq $0, 0
48 .section or,"x"
49 or $foo, %bx
50 orw $foo, bar
51 or $foo, %ebx
52 orl $foo, bar
53 or $foo, %rbx
54 orq $foo, bar
56 // CHECK: Disassembly of section xor:
57 // CHECK-EMPTY:
58 // CHECK-NEXT: <xor>:
59 // CHECK-NEXT: 0: 66 81 f3 00 00 xorw $0, %bx
60 // CHECK-NEXT: 5: 66 81 34 25 00 00 00 00 00 00 xorw $0, 0
61 // CHECK-NEXT: f: 81 f3 00 00 00 00 xorl $0, %ebx
62 // CHECK-NEXT: 15: 81 34 25 00 00 00 00 00 00 00 00 xorl $0, 0
63 // CHECK-NEXT: 20: 48 81 f3 00 00 00 00 xorq $0, %rbx
64 // CHECK-NEXT: 27: 48 81 34 25 00 00 00 00 00 00 00 00 xorq $0, 0
65 .section xor,"x"
66 xor $foo, %bx
67 xorw $foo, bar
68 xor $foo, %ebx
69 xorl $foo, bar
70 xor $foo, %rbx
71 xorq $foo, bar
73 // CHECK: Disassembly of section add:
74 // CHECK-EMPTY:
75 // CHECK-NEXT: <add>:
76 // CHECK-NEXT: 0: 66 81 c3 00 00 addw $0, %bx
77 // CHECK-NEXT: 5: 66 81 04 25 00 00 00 00 00 00 addw $0, 0
78 // CHECK-NEXT: f: 81 c3 00 00 00 00 addl $0, %ebx
79 // CHECK-NEXT: 15: 81 04 25 00 00 00 00 00 00 00 00 addl $0, 0
80 // CHECK-NEXT: 20: 48 81 c3 00 00 00 00 addq $0, %rbx
81 // CHECK-NEXT: 27: 48 81 04 25 00 00 00 00 00 00 00 00 addq $0, 0
82 .section add,"x"
83 add $foo, %bx
84 addw $foo, bar
85 add $foo, %ebx
86 addl $foo, bar
87 add $foo, %rbx
88 addq $foo, bar
90 // CHECK: Disassembly of section sub:
91 // CHECK-EMPTY:
92 // CHECK-NEXT: <sub>:
93 // CHECK-NEXT: 0: 66 81 eb 00 00 subw $0, %bx
94 // CHECK-NEXT: 5: 66 81 2c 25 00 00 00 00 00 00 subw $0, 0
95 // CHECK-NEXT: f: 81 eb 00 00 00 00 subl $0, %ebx
96 // CHECK-NEXT: 15: 81 2c 25 00 00 00 00 00 00 00 00 subl $0, 0
97 // CHECK-NEXT: 20: 48 81 eb 00 00 00 00 subq $0, %rbx
98 // CHECK-NEXT: 27: 48 81 2c 25 00 00 00 00 00 00 00 00 subq $0, 0
99 .section sub,"x"
100 sub $foo, %bx
101 subw $foo, bar
102 sub $foo, %ebx
103 subl $foo, bar
104 sub $foo, %rbx
105 subq $foo, bar
107 // CHECK: Disassembly of section cmp:
108 // CHECK-EMPTY:
109 // CHECK-NEXT: <cmp>:
110 // CHECK-NEXT: 0: 66 81 fb 00 00 cmpw $0, %bx
111 // CHECK-NEXT: 5: 66 81 3c 25 00 00 00 00 00 00 cmpw $0, 0
112 // CHECK-NEXT: f: 81 fb 00 00 00 00 cmpl $0, %ebx
113 // CHECK-NEXT: 15: 81 3c 25 00 00 00 00 00 00 00 00 cmpl $0, 0
114 // CHECK-NEXT: 20: 48 81 fb 00 00 00 00 cmpq $0, %rbx
115 // CHECK-NEXT: 27: 48 81 3c 25 00 00 00 00 00 00 00 00 cmpq $0, 0
116 .section cmp,"x"
117 cmp $foo, %bx
118 cmpw $foo, bar
119 cmp $foo, %ebx
120 cmpl $foo, bar
121 cmp $foo, %rbx
122 cmpq $foo, bar
124 // CHECK: Disassembly of section push:
125 // CHECK-EMPTY:
126 // CHECK-NEXT: <push>:
127 // CHECK-NEXT: 0: 66 68 00 00 pushw $0
128 // CHECK-NEXT: 4: 68 00 00 00 00 pushq $0
129 .section push,"x"
130 pushw $foo
131 push $foo
133 // CHECK: Disassembly of section adc:
134 // CHECK-EMPTY:
135 // CHECK-NEXT: <adc>:
136 // CHECK-NEXT: 0: 66 81 d3 00 00 adcw $0, %bx
137 // CHECK-NEXT: 5: 66 81 14 25 00 00 00 00 00 00 adcw $0, 0
138 // CHECK-NEXT: f: 81 d3 00 00 00 00 adcl $0, %ebx
139 // CHECK-NEXT: 15: 81 14 25 00 00 00 00 00 00 00 00 adcl $0, 0
140 // CHECK-NEXT: 20: 48 81 d3 00 00 00 00 adcq $0, %rbx
141 // CHECK-NEXT: 27: 48 81 14 25 00 00 00 00 00 00 00 00 adcq $0, 0
142 .section adc,"x"
143 adc $foo, %bx
144 adcw $foo, bar
145 adc $foo, %ebx
146 adcl $foo, bar
147 adc $foo, %rbx
148 adcq $foo, bar
150 // CHECK: Disassembly of section sbb:
151 // CHECK-EMPTY:
152 // CHECK-NEXT: <sbb>:
153 // CHECK-NEXT: 0: 66 81 db 00 00 sbbw $0, %bx
154 // CHECK-NEXT: 5: 66 81 1c 25 00 00 00 00 00 00 sbbw $0, 0
155 // CHECK-NEXT: f: 81 db 00 00 00 00 sbbl $0, %ebx
156 // CHECK-NEXT: 15: 81 1c 25 00 00 00 00 00 00 00 00 sbbl $0, 0
157 // CHECK-NEXT: 20: 48 81 db 00 00 00 00 sbbq $0, %rbx
158 // CHECK-NEXT: 27: 48 81 1c 25 00 00 00 00 00 00 00 00 sbbq $0, 0
159 .section sbb,"x"
160 sbb $foo, %bx
161 sbbw $foo, bar
162 sbb $foo, %ebx
163 sbbl $foo, bar
164 sbb $foo, %rbx
165 sbbq $foo, bar