1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s
3 ; Check that CodeGenPrepare transforms these functions to use
4 ; uadd.with.overflow / usub.with.overflow intrinsics so that the compare
5 ; instruction is eliminated.
7 define i32 @uaddo_32(i32 %arg) {
8 ; CHECK-LABEL: uaddo_32:
9 ; CHECK: alhsik %r0, %r2, -1
10 ; CHECK: locrnle %r2, %r0
14 %tmp10 = icmp ne i32 %arg, 0
15 %tmp11 = add nsw i32 %arg, -1
16 %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
20 define i64 @uaddo_64(i64 %arg) {
21 ; CHECK-LABEL: uaddo_64:
22 ; CHECK: alghsik %r0, %r2, -1
23 ; CHECK: locgrnle %r2, %r0
26 %tmp10 = icmp ne i64 %arg, 0
27 %tmp11 = add nsw i64 %arg, -1
28 %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
32 define i32 @usubo_32(i32 %arg) {
33 ; CHECK-LABEL: usubo_32:
34 ; CHECK: alhsik %r0, %r2, -1
35 ; CHECK: locrle %r2, %r0
38 %tmp10 = icmp eq i32 %arg, 0
39 %tmp11 = sub nsw i32 %arg, 1
40 %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
44 define i64 @usubo_64(i64 %arg) {
45 ; CHECK-LABEL: usubo_64:
46 ; CHECK: alghsik %r0, %r2, -1
47 ; CHECK: locgrle %r2, %r0
50 %tmp10 = icmp eq i64 %arg, 0
51 %tmp11 = sub nsw i64 %arg, 1
52 %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
56 define i32 @optbranch_32(i32 %Arg) {
57 ; CHECK-LABEL: optbranch_32:
58 ; CHECK: alhsik %r2, %r2, 1
59 ; CHECK-NEXT: bler %r14
60 ; CHECK-NEXT: .LBB4_1:
61 ; CHECK-NEXT: lhi %r2, -1
64 %i1 = icmp eq i32 %Arg, -1
65 br i1 %i1, label %bb2, label %bb3
71 %i4 = add nuw i32 %Arg, 1
75 define i64 @optbranch_64(i64 %Arg) {
76 ; CHECK-LABEL: optbranch_64:
77 ; CHECK: alghsik %r2, %r2, 1
78 ; CHECK-NEXT: bler %r14
79 ; CHECK-NEXT: .LBB5_1:
80 ; CHECK-NEXT: lghi %r2, -1
83 %i1 = icmp eq i64 %Arg, -1
84 br i1 %i1, label %bb2, label %bb3
90 %i4 = add nuw i64 %Arg, 1