1 // REQUIRES: arm-registered-target
2 // RUN: %clang_cc1 -triple armv7 -target-feature +neon %s -emit-llvm -o /dev/null
6 void t1(int x
, char y
) {
7 __asm__
volatile("mcr p15, 0, %1, c9, c12, 5;"
8 "mrc p15, 0, %0, c9, c13, 2;"
10 : "r" (bar())); // no warning
11 __asm__
volatile("foo %0, %1"
15 __asm__
volatile("ldrb %0, [%1]" : "=r" (y
) : "r" (x
)); // no warning
18 // <rdar://problem/12284092>
19 typedef __attribute__((neon_vector_type(2))) long long int64x2_t
;
20 typedef struct int64x2x4_t
{
23 int64x2x4_t
t2(const long long a
[]) {
25 __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
26 : [r0
] "=r"(r
.val
[0]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
27 [r1
] "=r"(r
.val
[1]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
28 [r2
] "=r"(r
.val
[2]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
29 [r3
] "=r"(r
.val
[3]) // expected-warning {{value size does not match register size specified by the constraint and modifier}}