llvm/lib/CodeGen/MachineRegisterInfo.cpp

   1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implementation of the MachineRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineRegisterInfo.h"
  14 #include "llvm/ADT/iterator_range.h"
  15 #include "llvm/CodeGen/MachineBasicBlock.h"
  16 #include "llvm/CodeGen/MachineFunction.h"
  17 #include "llvm/CodeGen/MachineInstr.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineOperand.h"
  20 #include "llvm/CodeGen/TargetInstrInfo.h"
  21 #include "llvm/CodeGen/TargetRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  23 #include "llvm/Config/llvm-config.h"
  24 #include "llvm/IR/Attributes.h"
  25 #include "llvm/IR/DebugLoc.h"
  26 #include "llvm/IR/Function.h"
  27 #include "llvm/MC/MCRegisterInfo.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Support/Compiler.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Support/raw_ostream.h"
  33 #include <cassert>
  34
  35 using namespace llvm;
  36
  37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
  38   cl::init(true), cl::desc("Enable subregister liveness tracking."));
  39
  40 // Pin the vtable to this file.
  41 void MachineRegisterInfo::Delegate::anchor() {}
  42
  43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
  44     : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
  45                                    EnableSubRegLiveness) {
  46   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
  47   VRegInfo.reserve(256);
  48   RegAllocHints.reserve(256);
  49   UsedPhysRegMask.resize(NumRegs);
  50   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
  51 }
  52
  53 /// setRegClass - Set the register class of the specified virtual register.
  54 ///
  55 void
  56 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
  57   assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
  58   VRegInfo[Reg].first = RC;
  59 }
  60
  61 void MachineRegisterInfo::setRegBank(Register Reg,
  62                                      const RegisterBank &RegBank) {
  63   VRegInfo[Reg].first = &RegBank;
  64 }
  65
  66 static const TargetRegisterClass *
  67 constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
  68                   const TargetRegisterClass *OldRC,
  69                   const TargetRegisterClass *RC, unsigned MinNumRegs) {
  70   if (OldRC == RC)
  71     return RC;
  72   const TargetRegisterClass *NewRC =
  73       MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
  74   if (!NewRC || NewRC == OldRC)
  75     return NewRC;
  76   if (NewRC->getNumRegs() < MinNumRegs)
  77     return nullptr;
  78   MRI.setRegClass(Reg, NewRC);
  79   return NewRC;
  80 }
  81
  82 const TargetRegisterClass *
  83 MachineRegisterInfo::constrainRegClass(Register Reg,
  84                                        const TargetRegisterClass *RC,
  85                                        unsigned MinNumRegs) {
  86   return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
  87 }
  88
  89 bool
  90 MachineRegisterInfo::constrainRegAttrs(Register Reg,
  91                                        Register ConstrainingReg,
  92                                        unsigned MinNumRegs) {
  93   const LLT RegTy = getType(Reg);
  94   const LLT ConstrainingRegTy = getType(ConstrainingReg);
  95   if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
  96       RegTy != ConstrainingRegTy)
  97     return false;
  98   const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
  99   if (!ConstrainingRegCB.isNull()) {
 100     const auto RegCB = getRegClassOrRegBank(Reg);
 101     if (RegCB.isNull())
 102       setRegClassOrRegBank(Reg, ConstrainingRegCB);
 103     else if (RegCB.is<const TargetRegisterClass *>() !=
 104              ConstrainingRegCB.is<const TargetRegisterClass *>())
 105       return false;
 106     else if (RegCB.is<const TargetRegisterClass *>()) {
 107       if (!::constrainRegClass(
 108               *this, Reg, RegCB.get<const TargetRegisterClass *>(),
 109               ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
 110         return false;
 111     } else if (RegCB != ConstrainingRegCB)
 112       return false;
 113   }
 114   if (ConstrainingRegTy.isValid())
 115     setType(Reg, ConstrainingRegTy);
 116   return true;
 117 }
 118
 119 bool
 120 MachineRegisterInfo::recomputeRegClass(Register Reg) {
 121   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 122   const TargetRegisterClass *OldRC = getRegClass(Reg);
 123   const TargetRegisterClass *NewRC =
 124       getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
 125
 126   // Stop early if there is no room to grow.
 127   if (NewRC == OldRC)
 128     return false;
 129
 130   // Accumulate constraints from all uses.
 131   for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
 132     // Apply the effect of the given operand to NewRC.
 133     MachineInstr *MI = MO.getParent();
 134     unsigned OpNo = &MO - &MI->getOperand(0);
 135     NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
 136                                             getTargetRegisterInfo());
 137     if (!NewRC || NewRC == OldRC)
 138       return false;
 139   }
 140   setRegClass(Reg, NewRC);
 141   return true;
 142 }
 143
 144 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
 145   Register Reg = Register::index2VirtReg(getNumVirtRegs());
 146   VRegInfo.grow(Reg);
 147   RegAllocHints.grow(Reg);
 148   insertVRegByName(Name, Reg);
 149   return Reg;
 150 }
 151
 152 /// createVirtualRegister - Create and return a new virtual register in the
 153 /// function with the specified register class.
 154 ///
 155 Register
 156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
 157                                            StringRef Name) {
 158   assert(RegClass && "Cannot create register without RegClass!");
 159   assert(RegClass->isAllocatable() &&
 160          "Virtual register RegClass must be allocatable.");
 161
 162   // New virtual register number.
 163   Register Reg = createIncompleteVirtualRegister(Name);
 164   VRegInfo[Reg].first = RegClass;
 165   if (TheDelegate)
 166     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 167   return Reg;
 168 }
 169
 170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
 171                                                    StringRef Name) {
 172   Register Reg = createIncompleteVirtualRegister(Name);
 173   VRegInfo[Reg].first = VRegInfo[VReg].first;
 174   setType(Reg, getType(VReg));
 175   if (TheDelegate)
 176     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 177   return Reg;
 178 }
 179
 180 void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
 181   VRegToType.grow(VReg);
 182   VRegToType[VReg] = Ty;
 183 }
 184
 185 Register
 186 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
 187   // New virtual register number.
 188   Register Reg = createIncompleteVirtualRegister(Name);
 189   // FIXME: Should we use a dummy register class?
 190   VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
 191   setType(Reg, Ty);
 192   if (TheDelegate)
 193     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 194   return Reg;
 195 }
 196
 197 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
 198
 199 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
 200 void MachineRegisterInfo::clearVirtRegs() {
 201 #ifndef NDEBUG
 202   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
 203     Register Reg = Register::index2VirtReg(i);
 204     if (!VRegInfo[Reg].second)
 205       continue;
 206     verifyUseList(Reg);
 207     llvm_unreachable("Remaining virtual register operands");
 208   }
 209 #endif
 210   VRegInfo.clear();
 211   for (auto &I : LiveIns)
 212     I.second = 0;
 213 }
 214
 215 void MachineRegisterInfo::verifyUseList(Register Reg) const {
 216 #ifndef NDEBUG
 217   bool Valid = true;
 218   for (MachineOperand &M : reg_operands(Reg)) {
 219     MachineOperand *MO = &M;
 220     MachineInstr *MI = MO->getParent();
 221     if (!MI) {
 222       errs() << printReg(Reg, getTargetRegisterInfo())
 223              << " use list MachineOperand " << MO
 224              << " has no parent instruction.\n";
 225       Valid = false;
 226       continue;
 227     }
 228     MachineOperand *MO0 = &MI->getOperand(0);
 229     unsigned NumOps = MI->getNumOperands();
 230     if (!(MO >= MO0 && MO < MO0+NumOps)) {
 231       errs() << printReg(Reg, getTargetRegisterInfo())
 232              << " use list MachineOperand " << MO
 233              << " doesn't belong to parent MI: " << *MI;
 234       Valid = false;
 235     }
 236     if (!MO->isReg()) {
 237       errs() << printReg(Reg, getTargetRegisterInfo())
 238              << " MachineOperand " << MO << ": " << *MO
 239              << " is not a register\n";
 240       Valid = false;
 241     }
 242     if (MO->getReg() != Reg) {
 243       errs() << printReg(Reg, getTargetRegisterInfo())
 244              << " use-list MachineOperand " << MO << ": "
 245              << *MO << " is the wrong register\n";
 246       Valid = false;
 247     }
 248   }
 249   assert(Valid && "Invalid use list");
 250 #endif
 251 }
 252
 253 void MachineRegisterInfo::verifyUseLists() const {
 254 #ifndef NDEBUG
 255   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
 256     verifyUseList(Register::index2VirtReg(i));
 257   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
 258     verifyUseList(i);
 259 #endif
 260 }
 261
 262 /// Add MO to the linked list of operands for its register.
 263 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
 264   assert(!MO->isOnRegUseList() && "Already on list");
 265   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 266   MachineOperand *const Head = HeadRef;
 267
 268   // Head points to the first list element.
 269   // Next is NULL on the last list element.
 270   // Prev pointers are circular, so Head->Prev == Last.
 271
 272   // Head is NULL for an empty list.
 273   if (!Head) {
 274     MO->Contents.Reg.Prev = MO;
 275     MO->Contents.Reg.Next = nullptr;
 276     HeadRef = MO;
 277     return;
 278   }
 279   assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
 280
 281   // Insert MO between Last and Head in the circular Prev chain.
 282   MachineOperand *Last = Head->Contents.Reg.Prev;
 283   assert(Last && "Inconsistent use list");
 284   assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
 285   Head->Contents.Reg.Prev = MO;
 286   MO->Contents.Reg.Prev = Last;
 287
 288   // Def operands always precede uses. This allows def_iterator to stop early.
 289   // Insert def operands at the front, and use operands at the back.
 290   if (MO->isDef()) {
 291     // Insert def at the front.
 292     MO->Contents.Reg.Next = Head;
 293     HeadRef = MO;
 294   } else {
 295     // Insert use at the end.
 296     MO->Contents.Reg.Next = nullptr;
 297     Last->Contents.Reg.Next = MO;
 298   }
 299 }
 300
 301 /// Remove MO from its use-def list.
 302 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
 303   assert(MO->isOnRegUseList() && "Operand not on use list");
 304   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 305   MachineOperand *const Head = HeadRef;
 306   assert(Head && "List already empty");
 307
 308   // Unlink this from the doubly linked list of operands.
 309   MachineOperand *Next = MO->Contents.Reg.Next;
 310   MachineOperand *Prev = MO->Contents.Reg.Prev;
 311
 312   // Prev links are circular, next link is NULL instead of looping back to Head.
 313   if (MO == Head)
 314     HeadRef = Next;
 315   else
 316     Prev->Contents.Reg.Next = Next;
 317
 318   (Next ? Next : Head)->Contents.Reg.Prev = Prev;
 319
 320   MO->Contents.Reg.Prev = nullptr;
 321   MO->Contents.Reg.Next = nullptr;
 322 }
 323
 324 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
 325 ///
 326 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
 327 /// operands that won't be destroyed, which is OK because the MO destructor is
 328 /// trivial anyway).
 329 ///
 330 /// The Src and Dst ranges may overlap.
 331 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
 332                                        MachineOperand *Src,
 333                                        unsigned NumOps) {
 334   assert(Src != Dst && NumOps && "Noop moveOperands");
 335
 336   // Copy backwards if Dst is within the Src range.
 337   int Stride = 1;
 338   if (Dst >= Src && Dst < Src + NumOps) {
 339     Stride = -1;
 340     Dst += NumOps - 1;
 341     Src += NumOps - 1;
 342   }
 343
 344   // Copy one operand at a time.
 345   do {
 346     new (Dst) MachineOperand(*Src);
 347
 348     // Dst takes Src's place in the use-def chain.
 349     if (Src->isReg()) {
 350       MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
 351       MachineOperand *Prev = Src->Contents.Reg.Prev;
 352       MachineOperand *Next = Src->Contents.Reg.Next;
 353       assert(Head && "List empty, but operand is chained");
 354       assert(Prev && "Operand was not on use-def list");
 355
 356       // Prev links are circular, next link is NULL instead of looping back to
 357       // Head.
 358       if (Src == Head)
 359         Head = Dst;
 360       else
 361         Prev->Contents.Reg.Next = Dst;
 362
 363       // Update Prev pointer. This also works when Src was pointing to itself
 364       // in a 1-element list. In that case Head == Dst.
 365       (Next ? Next : Head)->Contents.Reg.Prev = Dst;
 366     }
 367
 368     Dst += Stride;
 369     Src += Stride;
 370   } while (--NumOps);
 371 }
 372
 373 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 374 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 375 /// except that it also changes any definitions of the register as well.
 376 /// If ToReg is a physical register we apply the sub register to obtain the
 377 /// final/proper physical register.
 378 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
 379   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 380
 381   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 382
 383   // TODO: This could be more efficient by bulk changing the operands.
 384   for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {
 385     if (Register::isPhysicalRegister(ToReg)) {
 386       O.substPhysReg(ToReg, *TRI);
 387     } else {
 388       O.setReg(ToReg);
 389     }
 390   }
 391 }
 392
 393 /// getVRegDef - Return the machine instr that defines the specified virtual
 394 /// register or null if none is found.  This assumes that the code is in SSA
 395 /// form, so there should only be one definition.
 396 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
 397   // Since we are in SSA form, we can use the first definition.
 398   def_instr_iterator I = def_instr_begin(Reg);
 399   assert((I.atEnd() || std::next(I) == def_instr_end()) &&
 400          "getVRegDef assumes a single definition or no definition");
 401   return !I.atEnd() ? &*I : nullptr;
 402 }
 403
 404 /// getUniqueVRegDef - Return the unique machine instr that defines the
 405 /// specified virtual register or null if none is found.  If there are
 406 /// multiple definitions or no definition, return null.
 407 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
 408   if (def_empty(Reg)) return nullptr;
 409   def_instr_iterator I = def_instr_begin(Reg);
 410   if (std::next(I) != def_instr_end())
 411     return nullptr;
 412   return &*I;
 413 }
 414
 415 bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
 416   return hasSingleElement(use_nodbg_operands(RegNo));
 417 }
 418
 419 bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
 420   return hasSingleElement(use_nodbg_instructions(RegNo));
 421 }
 422
 423 bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg,
 424                                               unsigned MaxUsers) const {
 425   return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(),
 426                          MaxUsers);
 427 }
 428
 429 /// clearKillFlags - Iterate over all the uses of the given register and
 430 /// clear the kill flag from the MachineOperand. This function is used by
 431 /// optimization passes which extend register lifetimes and need only
 432 /// preserve conservative kill flag information.
 433 void MachineRegisterInfo::clearKillFlags(Register Reg) const {
 434   for (MachineOperand &MO : use_operands(Reg))
 435     MO.setIsKill(false);
 436 }
 437
 438 bool MachineRegisterInfo::isLiveIn(Register Reg) const {
 439   for (const std::pair<MCRegister, Register> &LI : liveins())
 440     if ((Register)LI.first == Reg || LI.second == Reg)
 441       return true;
 442   return false;
 443 }
 444
 445 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 446 /// corresponding live-in physical register.
 447 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
 448   for (const std::pair<MCRegister, Register> &LI : liveins())
 449     if (LI.second == VReg)
 450       return LI.first;
 451   return MCRegister();
 452 }
 453
 454 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 455 /// corresponding live-in physical register.
 456 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
 457   for (const std::pair<MCRegister, Register> &LI : liveins())
 458     if (LI.first == PReg)
 459       return LI.second;
 460   return Register();
 461 }
 462
 463 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 464 /// into the given entry block.
 465 void
 466 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 467                                       const TargetRegisterInfo &TRI,
 468                                       const TargetInstrInfo &TII) {
 469   // Emit the copies into the top of the block.
 470   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 471     if (LiveIns[i].second) {
 472       if (use_nodbg_empty(LiveIns[i].second)) {
 473         // The livein has no non-dbg uses. Drop it.
 474         //
 475         // It would be preferable to have isel avoid creating live-in
 476         // records for unused arguments in the first place, but it's
 477         // complicated by the debug info code for arguments.
 478         LiveIns.erase(LiveIns.begin() + i);
 479         --i; --e;
 480       } else {
 481         // Emit a copy.
 482         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
 483                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 484           .addReg(LiveIns[i].first);
 485
 486         // Add the register to the entry block live-in set.
 487         EntryMBB->addLiveIn(LiveIns[i].first);
 488       }
 489     } else {
 490       // Add the register to the entry block live-in set.
 491       EntryMBB->addLiveIn(LiveIns[i].first);
 492     }
 493 }
 494
 495 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
 496   // Lane masks are only defined for vregs.
 497   assert(Register::isVirtualRegister(Reg));
 498   const TargetRegisterClass &TRC = *getRegClass(Reg);
 499   return TRC.getLaneMask();
 500 }
 501
 502 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 503 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
 504   for (MachineInstr &I : use_instructions(Reg))
 505     I.dump();
 506 }
 507 #endif
 508
 509 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
 510   ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
 511   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
 512          "Invalid ReservedRegs vector from target");
 513 }
 514
 515 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
 516   assert(Register::isPhysicalRegister(PhysReg));
 517
 518   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 519   if (TRI->isConstantPhysReg(PhysReg))
 520     return true;
 521
 522   // Check if any overlapping register is modified, or allocatable so it may be
 523   // used later.
 524   for (MCRegAliasIterator AI(PhysReg, TRI, true);
 525        AI.isValid(); ++AI)
 526     if (!def_empty(*AI) || isAllocatable(*AI))
 527       return false;
 528   return true;
 529 }
 530
 531 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
 532 /// specified register as undefined which causes the DBG_VALUE to be
 533 /// deleted during LiveDebugVariables analysis.
 534 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
 535   // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
 536   // We use make_early_inc_range because setReg invalidates the iterator.
 537   for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {
 538     if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
 539       UseMI.setDebugValueUndef();
 540   }
 541 }
 542
 543 static const Function *getCalledFunction(const MachineInstr &MI) {
 544   for (const MachineOperand &MO : MI.operands()) {
 545     if (!MO.isGlobal())
 546       continue;
 547     const Function *Func = dyn_cast<Function>(MO.getGlobal());
 548     if (Func != nullptr)
 549       return Func;
 550   }
 551   return nullptr;
 552 }
 553
 554 static bool isNoReturnDef(const MachineOperand &MO) {
 555   // Anything which is not a noreturn function is a real def.
 556   const MachineInstr &MI = *MO.getParent();
 557   if (!MI.isCall())
 558     return false;
 559   const MachineBasicBlock &MBB = *MI.getParent();
 560   if (!MBB.succ_empty())
 561     return false;
 562   const MachineFunction &MF = *MBB.getParent();
 563   // We need to keep correct unwind information even if the function will
 564   // not return, since the runtime may need it.
 565   if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
 566     return false;
 567   const Function *Called = getCalledFunction(MI);
 568   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
 569            !Called->hasFnAttribute(Attribute::NoUnwind));
 570 }
 571
 572 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
 573                                             bool SkipNoReturnDef) const {
 574   if (UsedPhysRegMask.test(PhysReg))
 575     return true;
 576   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 577   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
 578     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
 579       if (!SkipNoReturnDef && isNoReturnDef(MO))
 580         continue;
 581       return true;
 582     }
 583   }
 584   return false;
 585 }
 586
 587 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
 588                                         bool SkipRegMaskTest) const {
 589   if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
 590     return true;
 591   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 592   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
 593        ++AliasReg) {
 594     if (!reg_nodbg_empty(*AliasReg))
 595       return true;
 596   }
 597   return false;
 598 }
 599
 600 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
 601
 602   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 603   assert(Reg && (Reg < TRI->getNumRegs()) &&
 604          "Trying to disable an invalid register");
 605
 606   if (!IsUpdatedCSRsInitialized) {
 607     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
 608     for (const MCPhysReg *I = CSR; *I; ++I)
 609       UpdatedCSRs.push_back(*I);
 610
 611     // Zero value represents the end of the register list
 612     // (no more registers should be pushed).
 613     UpdatedCSRs.push_back(0);
 614
 615     IsUpdatedCSRsInitialized = true;
 616   }
 617
 618   // Remove the register (and its aliases from the list).
 619   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 620     llvm::erase_value(UpdatedCSRs, *AI);
 621 }
 622
 623 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
 624   if (IsUpdatedCSRsInitialized)
 625     return UpdatedCSRs.data();
 626
 627   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
 628 }
 629
 630 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
 631   if (IsUpdatedCSRsInitialized)
 632     UpdatedCSRs.clear();
 633
 634   append_range(UpdatedCSRs, CSRs);
 635
 636   // Zero value represents the end of the register list
 637   // (no more registers should be pushed).
 638   UpdatedCSRs.push_back(0);
 639   IsUpdatedCSRsInitialized = true;
 640 }
 641
 642 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
 643   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 644   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
 645     bool IsRootReserved = true;
 646     for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
 647          Super.isValid(); ++Super) {
 648       MCRegister Reg = *Super;
 649       if (!isReserved(Reg)) {
 650         IsRootReserved = false;
 651         break;
 652       }
 653     }
 654     if (IsRootReserved)
 655       return true;
 656   }
 657   return false;
 658 }
 659
 660 bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF,
 661                                              MCRegister Reg) const {
 662   return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
 663 }
 664
 665 bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF,
 666                                           MCRegister Reg) const {
 667   return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
 668 }
 669
 670 bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF,
 671                                                    MCRegister Reg) const {
 672   return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg);
 673 }