llvm/lib/CodeGen/RegisterClassInfo.cpp

   1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the RegisterClassInfo class which provides dynamic
  10 // information about target register classes. Callee-saved vs. caller-saved and
  11 // reserved registers depend on calling conventions and other dynamic
  12 // information, so some things cannot be determined statically.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "llvm/CodeGen/RegisterClassInfo.h"
  17 #include "llvm/ADT/ArrayRef.h"
  18 #include "llvm/ADT/BitVector.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetRegisterInfo.h"
  23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  24 #include "llvm/MC/MCRegisterInfo.h"
  25 #include "llvm/Support/CommandLine.h"
  26 #include "llvm/Support/Debug.h"
  27 #include "llvm/Support/raw_ostream.h"
  28 #include <algorithm>
  29 #include <cassert>
  30 #include <cstdint>
  31
  32 using namespace llvm;
  33
  34 #define DEBUG_TYPE "regalloc"
  35
  36 static cl::opt<unsigned>
  37 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
  38          cl::desc("Limit all regclasses to N registers"));
  39
  40 RegisterClassInfo::RegisterClassInfo() = default;
  41
  42 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
  43   bool Update = false;
  44   MF = &mf;
  45
  46   auto &STI = MF->getSubtarget();
  47
  48   // Allocate new array the first time we see a new target.
  49   if (STI.getRegisterInfo() != TRI) {
  50     TRI = STI.getRegisterInfo();
  51     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
  52     Update = true;
  53   }
  54
  55   // Test if CSRs have changed from the previous function.
  56   const MachineRegisterInfo &MRI = MF->getRegInfo();
  57   const MCPhysReg *CSR = MRI.getCalleeSavedRegs();
  58   bool CSRChanged = true;
  59   if (!Update) {
  60     CSRChanged = false;
  61     size_t LastSize = LastCalleeSavedRegs.size();
  62     for (unsigned I = 0;; ++I) {
  63       if (CSR[I] == 0 || I >= LastSize) {
  64         CSRChanged = I != LastSize;
  65         break;
  66       }
  67       if (CSR[I] != LastCalleeSavedRegs[I]) {
  68         CSRChanged = true;
  69         break;
  70       }
  71     }
  72   }
  73
  74   // Get the callee saved registers.
  75   if (CSRChanged) {
  76     LastCalleeSavedRegs.clear();
  77     // Build a CSRAlias map. Every CSR alias saves the last
  78     // overlapping CSR.
  79     CalleeSavedAliases.assign(TRI->getNumRegs(), 0);
  80     for (const MCPhysReg *I = CSR; *I; ++I) {
  81       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
  82         CalleeSavedAliases[*AI] = *I;
  83       LastCalleeSavedRegs.push_back(*I);
  84     }
  85
  86     Update = true;
  87   }
  88
  89   // Even if CSR list is same, we could have had a different allocation order
  90   // if ignoreCSRForAllocationOrder is evaluated differently.
  91   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
  92   for (const MCPhysReg *I = CSR; *I; ++I)
  93     for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
  94       CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
  95   if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
  96       IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
  97     Update = true;
  98     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
  99   }
 100
 101   RegCosts = TRI->getRegisterCosts(*MF);
 102
 103   // Different reserved registers?
 104   const BitVector &RR = MF->getRegInfo().getReservedRegs();
 105   if (Reserved.size() != RR.size() || RR != Reserved) {
 106     Update = true;
 107     Reserved = RR;
 108   }
 109
 110   // Invalidate cached information from previous function.
 111   if (Update) {
 112     unsigned NumPSets = TRI->getNumRegPressureSets();
 113     PSetLimits.reset(new unsigned[NumPSets]);
 114     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
 115     ++Tag;
 116   }
 117 }
 118
 119 /// compute - Compute the preferred allocation order for RC with reserved
 120 /// registers filtered out. Volatile registers come first followed by CSR
 121 /// aliases ordered according to the CSR order specified by the target.
 122 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
 123   assert(RC && "no register class given");
 124   RCInfo &RCI = RegClass[RC->getID()];
 125   auto &STI = MF->getSubtarget();
 126
 127   // Raw register count, including all reserved regs.
 128   unsigned NumRegs = RC->getNumRegs();
 129
 130   if (!RCI.Order)
 131     RCI.Order.reset(new MCPhysReg[NumRegs]);
 132
 133   unsigned N = 0;
 134   SmallVector<MCPhysReg, 16> CSRAlias;
 135   uint8_t MinCost = uint8_t(~0u);
 136   uint8_t LastCost = uint8_t(~0u);
 137   unsigned LastCostChange = 0;
 138
 139   // FIXME: Once targets reserve registers instead of removing them from the
 140   // allocation order, we can simply use begin/end here.
 141   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
 142   for (unsigned PhysReg : RawOrder) {
 143     // Remove reserved registers from the allocation order.
 144     if (Reserved.test(PhysReg))
 145       continue;
 146     uint8_t Cost = RegCosts[PhysReg];
 147     MinCost = std::min(MinCost, Cost);
 148
 149     if (CalleeSavedAliases[PhysReg] &&
 150         !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
 151       // PhysReg aliases a CSR, save it for later.
 152       CSRAlias.push_back(PhysReg);
 153     else {
 154       if (Cost != LastCost)
 155         LastCostChange = N;
 156       RCI.Order[N++] = PhysReg;
 157       LastCost = Cost;
 158     }
 159   }
 160   RCI.NumRegs = N + CSRAlias.size();
 161   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
 162
 163   // CSR aliases go after the volatile registers, preserve the target's order.
 164   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
 165     unsigned PhysReg = CSRAlias[i];
 166     uint8_t Cost = RegCosts[PhysReg];
 167     if (Cost != LastCost)
 168       LastCostChange = N;
 169     RCI.Order[N++] = PhysReg;
 170     LastCost = Cost;
 171   }
 172
 173   // Register allocator stress test.  Clip register class to N registers.
 174   if (StressRA && RCI.NumRegs > StressRA)
 175     RCI.NumRegs = StressRA;
 176
 177   // Check if RC is a proper sub-class.
 178   if (const TargetRegisterClass *Super =
 179           TRI->getLargestLegalSuperClass(RC, *MF))
 180     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
 181       RCI.ProperSubClass = true;
 182
 183   RCI.MinCost = MinCost;
 184   RCI.LastCostChange = LastCostChange;
 185
 186   LLVM_DEBUG({
 187     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
 188     for (unsigned I = 0; I != RCI.NumRegs; ++I)
 189       dbgs() << ' ' << printReg(RCI.Order[I], TRI);
 190     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
 191   });
 192
 193   // RCI is now up-to-date.
 194   RCI.Tag = Tag;
 195 }
 196
 197 /// This is not accurate because two overlapping register sets may have some
 198 /// nonoverlapping reserved registers. However, computing the allocation order
 199 /// for all register classes would be too expensive.
 200 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
 201   const TargetRegisterClass *RC = nullptr;
 202   unsigned NumRCUnits = 0;
 203   for (const TargetRegisterClass *C : TRI->regclasses()) {
 204     const int *PSetID = TRI->getRegClassPressureSets(C);
 205     for (; *PSetID != -1; ++PSetID) {
 206       if ((unsigned)*PSetID == Idx)
 207         break;
 208     }
 209     if (*PSetID == -1)
 210       continue;
 211
 212     // Found a register class that counts against this pressure set.
 213     // For efficiency, only compute the set order for the largest set.
 214     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
 215     if (!RC || NUnits > NumRCUnits) {
 216       RC = C;
 217       NumRCUnits = NUnits;
 218     }
 219   }
 220   assert(RC && "Failed to find register class");
 221   compute(RC);
 222   unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
 223   unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
 224   // If all the regs are reserved, return raw RegPressureSetLimit.
 225   // One example is VRSAVERC in PowerPC.
 226   // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
 227   // return non-zero value.
 228   if (NAllocatableRegs == 0)
 229     return RegPressureSetLimit;
 230   unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
 231   return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
 232 }