1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
4 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5 target triple = "thumbv8m.base-none-none-eabi"
7 define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
8 define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
9 define i32 @test_subri3(i32 %a) { ret i32 %a }
10 define i32 @test_subri8(i32 %a) { ret i32 %a }
11 define i32 @test_addrr(i32 %a) { ret i32 %a }
12 define i32 @test_addri3(i32 %a) { ret i32 %a }
13 define i32 @test_addri8(i32 %a) { ret i32 %a }
19 - { reg: '$r0', virtual-reg: '%1' }
20 - { reg: '$r1', virtual-reg: '%2' }
22 ; CHECK-LABEL: name: test_subrr
24 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
25 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
26 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
27 ; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
28 ; CHECK: tBcc %bb.2, 8 /* CC::hi */, $cpsr
29 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
31 ; CHECK: $r0 = COPY %2
32 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
34 ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
35 ; CHECK: $r0 = COPY %3
36 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
38 successors: %bb.2(0x40000000), %bb.1(0x40000000)
43 %0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
44 tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
50 tBX_RET 14, $noreg, implicit $r0
53 %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
55 tBX_RET 14, $noreg, implicit $r0
61 - { reg: '$r0', virtual-reg: '%1' }
62 - { reg: '$r1', virtual-reg: '%2' }
64 ; CHECK-LABEL: name: test_subrr_c
66 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
67 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
68 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
69 ; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
70 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
71 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
73 ; CHECK: $r0 = COPY %2
74 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
76 ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
77 ; CHECK: $r0 = COPY %3
78 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
80 successors: %bb.2(0x40000000), %bb.1(0x40000000)
85 %0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
86 tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
92 tBX_RET 14, $noreg, implicit $r0
95 %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
97 tBX_RET 14, $noreg, implicit $r0
103 - { reg: '$r0', virtual-reg: '%1' }
105 ; CHECK-LABEL: name: test_subri3
107 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
108 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
109 ; CHECK: %1:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14 /* CC::al */, $noreg
110 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
111 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
113 ; CHECK: $r0 = COPY %1
114 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
116 ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
117 ; CHECK: $r0 = COPY %2
118 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
120 successors: %bb.2(0x40000000), %bb.1(0x40000000)
124 %0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
125 tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
131 tBX_RET 14, $noreg, implicit $r0
134 %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
136 tBX_RET 14, $noreg, implicit $r0
142 - { reg: '$r0', virtual-reg: '%1' }
144 ; CHECK-LABEL: name: test_subri8
146 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
147 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
148 ; CHECK: %1:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14 /* CC::al */, $noreg
149 ; CHECK: tBcc %bb.2, 3 /* CC::lo */, $cpsr
150 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
152 ; CHECK: $r0 = COPY %1
153 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
155 ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
156 ; CHECK: $r0 = COPY %2
157 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
159 successors: %bb.2(0x40000000), %bb.1(0x40000000)
163 %0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
164 tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
170 tBX_RET 14, $noreg, implicit $r0
173 %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
175 tBX_RET 14, $noreg, implicit $r0
181 - { reg: '$r0', virtual-reg: '%1' }
182 - { reg: '$r1', virtual-reg: '%2' }
184 ; CHECK-LABEL: name: test_addrr
186 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
187 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
188 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
189 ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
190 ; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
191 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
193 ; CHECK: $r0 = COPY %2
194 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
196 ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
197 ; CHECK: $r0 = COPY %3
198 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
200 successors: %bb.2(0x40000000), %bb.1(0x40000000)
205 %0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
206 tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
212 tBX_RET 14, $noreg, implicit $r0
215 %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
217 tBX_RET 14, $noreg, implicit $r0
223 - { reg: '$r0', virtual-reg: '%1' }
225 ; CHECK-LABEL: name: test_addri3
227 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
228 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
229 ; CHECK: %0:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14 /* CC::al */, $noreg
230 ; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
231 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
233 ; CHECK: $r0 = COPY [[COPY]]
234 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
236 ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
237 ; CHECK: $r0 = COPY %2
238 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
240 successors: %bb.2(0x40000000), %bb.1(0x40000000)
244 %1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
245 tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
251 tBX_RET 14, $noreg, implicit $r0
254 %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
256 tBX_RET 14, $noreg, implicit $r0
262 - { reg: '$r0', virtual-reg: '%1' }
264 ; CHECK-LABEL: name: test_addri8
266 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
267 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
268 ; CHECK: %0:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14 /* CC::al */, $noreg
269 ; CHECK: tBcc %bb.2, 2 /* CC::hs */, $cpsr
270 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
272 ; CHECK: $r0 = COPY [[COPY]]
273 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
275 ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
276 ; CHECK: $r0 = COPY %2
277 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
279 successors: %bb.2(0x40000000), %bb.1(0x40000000)
283 %1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
284 tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
290 tBX_RET 14, $noreg, implicit $r0
293 %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
295 tBX_RET 14, $noreg, implicit $r0