1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -S %s -scalarize-masked-mem-intrin -mtriple=aarch64-linux-gnu | FileCheck -check-prefixes=CHECK,CHECK-LE %s
3 ; RUN: opt -S %s -scalarize-masked-mem-intrin -mtriple=aarch64-linux-gnu -mattr=+sve | FileCheck -check-prefixes=CHECK,CHECK-LE %s
4 ; RUN: opt -S %s -scalarize-masked-mem-intrin -mtriple=aarch64_be-linux-gnu -data-layout="E-m:o-i64:64-i128:128-n32:64-S128" | FileCheck -check-prefixes=CHECK,CHECK-BE %s
6 define void @scalarize_v2i64(<2 x i64>* %p, <2 x i1> %mask, <2 x i64> %data) {
7 ; CHECK-LE-LABEL: @scalarize_v2i64(
8 ; CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64>* [[P:%.*]] to i64*
9 ; CHECK-LE-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK:%.*]] to i2
10 ; CHECK-LE-NEXT: [[TMP2:%.*]] = and i2 [[SCALAR_MASK]], 1
11 ; CHECK-LE-NEXT: [[TMP3:%.*]] = icmp ne i2 [[TMP2]], 0
12 ; CHECK-LE-NEXT: br i1 [[TMP3]], label [[COND_STORE:%.*]], label [[ELSE:%.*]]
13 ; CHECK-LE: cond.store:
14 ; CHECK-LE-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[DATA:%.*]], i64 0
15 ; CHECK-LE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 0
16 ; CHECK-LE-NEXT: store i64 [[TMP4]], i64* [[TMP5]], align 8
17 ; CHECK-LE-NEXT: br label [[ELSE]]
19 ; CHECK-LE-NEXT: [[TMP6:%.*]] = and i2 [[SCALAR_MASK]], -2
20 ; CHECK-LE-NEXT: [[TMP7:%.*]] = icmp ne i2 [[TMP6]], 0
21 ; CHECK-LE-NEXT: br i1 [[TMP7]], label [[COND_STORE1:%.*]], label [[ELSE2:%.*]]
22 ; CHECK-LE: cond.store1:
23 ; CHECK-LE-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[DATA]], i64 1
24 ; CHECK-LE-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 1
25 ; CHECK-LE-NEXT: store i64 [[TMP8]], i64* [[TMP9]], align 8
26 ; CHECK-LE-NEXT: br label [[ELSE2]]
28 ; CHECK-LE-NEXT: ret void
30 ; CHECK-BE-LABEL: @scalarize_v2i64(
31 ; CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64>* [[P:%.*]] to i64*
32 ; CHECK-BE-NEXT: [[SCALAR_MASK:%.*]] = bitcast <2 x i1> [[MASK:%.*]] to i2
33 ; CHECK-BE-NEXT: [[TMP2:%.*]] = and i2 [[SCALAR_MASK]], -2
34 ; CHECK-BE-NEXT: [[TMP3:%.*]] = icmp ne i2 [[TMP2]], 0
35 ; CHECK-BE-NEXT: br i1 [[TMP3]], label [[COND_STORE:%.*]], label [[ELSE:%.*]]
36 ; CHECK-BE: cond.store:
37 ; CHECK-BE-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[DATA:%.*]], i64 0
38 ; CHECK-BE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 0
39 ; CHECK-BE-NEXT: store i64 [[TMP4]], i64* [[TMP5]], align 8
40 ; CHECK-BE-NEXT: br label [[ELSE]]
42 ; CHECK-BE-NEXT: [[TMP6:%.*]] = and i2 [[SCALAR_MASK]], 1
43 ; CHECK-BE-NEXT: [[TMP7:%.*]] = icmp ne i2 [[TMP6]], 0
44 ; CHECK-BE-NEXT: br i1 [[TMP7]], label [[COND_STORE1:%.*]], label [[ELSE2:%.*]]
45 ; CHECK-BE: cond.store1:
46 ; CHECK-BE-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[DATA]], i64 1
47 ; CHECK-BE-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 1
48 ; CHECK-BE-NEXT: store i64 [[TMP8]], i64* [[TMP9]], align 8
49 ; CHECK-BE-NEXT: br label [[ELSE2]]
51 ; CHECK-BE-NEXT: ret void
53 call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %data, <2 x i64>* %p, i32 128, <2 x i1> %mask)
57 define void @scalarize_v2i64_ones_mask(<2 x i64>* %p, <2 x i64> %data) {
58 ; CHECK-LABEL: @scalarize_v2i64_ones_mask(
59 ; CHECK-NEXT: store <2 x i64> [[DATA:%.*]], <2 x i64>* [[P:%.*]], align 8
60 ; CHECK-NEXT: ret void
62 call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %data, <2 x i64>* %p, i32 8, <2 x i1> <i1 true, i1 true>)
66 define void @scalarize_v2i64_zero_mask(<2 x i64>* %p, <2 x i64> %data) {
67 ; CHECK-LABEL: @scalarize_v2i64_zero_mask(
68 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64>* [[P:%.*]] to i64*
69 ; CHECK-NEXT: ret void
71 call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %data, <2 x i64>* %p, i32 8, <2 x i1> <i1 false, i1 false>)
75 define void @scalarize_v2i64_const_mask(<2 x i64>* %p, <2 x i64> %data) {
76 ; CHECK-LABEL: @scalarize_v2i64_const_mask(
77 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64>* [[P:%.*]] to i64*
78 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[DATA:%.*]], i64 1
79 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 1
80 ; CHECK-NEXT: store i64 [[TMP2]], i64* [[TMP3]], align 8
81 ; CHECK-NEXT: ret void
83 call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %data, <2 x i64>* %p, i32 8, <2 x i1> <i1 false, i1 true>)
87 declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)