llvm/lib/Target/AMDGPU/SIDefines.h

   1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 /// \file
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
  11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
  12
  13 #include "llvm/MC/MCInstrDesc.h"
  14
  15 namespace llvm {
  16
  17 // This needs to be kept in sync with the field bits in SIRegisterClass.
  18 enum SIRCFlags : uint8_t {
  19   RegTupleAlignUnitsWidth = 2,
  20   HasVGPRBit = RegTupleAlignUnitsWidth,
  21   HasAGPRBit,
  22   HasSGPRbit,
  23
  24   HasVGPR = 1 << HasVGPRBit,
  25   HasAGPR = 1 << HasAGPRBit,
  26   HasSGPR = 1 << HasSGPRbit,
  27
  28   RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
  29   RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
  30 }; // enum SIRCFlagsr
  31
  32 namespace SIEncodingFamily {
  33 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
  34 // and the columns of the getMCOpcodeGen table.
  35 enum {
  36   SI = 0,
  37   VI = 1,
  38   SDWA = 2,
  39   SDWA9 = 3,
  40   GFX80 = 4,
  41   GFX9 = 5,
  42   GFX10 = 6,
  43   SDWA10 = 7,
  44   GFX90A = 8,
  45   GFX940 = 9,
  46   GFX11 = 10,
  47   GFX12 = 11,
  48 };
  49 }
  50
  51 namespace SIInstrFlags {
  52 // This needs to be kept in sync with the field bits in InstSI.
  53 enum : uint64_t {
  54   // Low bits - basic encoding information.
  55   SALU = 1 << 0,
  56   VALU = 1 << 1,
  57
  58   // SALU instruction formats.
  59   SOP1 = 1 << 2,
  60   SOP2 = 1 << 3,
  61   SOPC = 1 << 4,
  62   SOPK = 1 << 5,
  63   SOPP = 1 << 6,
  64
  65   // VALU instruction formats.
  66   VOP1 = 1 << 7,
  67   VOP2 = 1 << 8,
  68   VOPC = 1 << 9,
  69
  70   // TODO: Should this be spilt into VOP3 a and b?
  71   VOP3 = 1 << 10,
  72   VOP3P = 1 << 12,
  73
  74   VINTRP = 1 << 13,
  75   SDWA = 1 << 14,
  76   DPP = 1 << 15,
  77   TRANS = 1 << 16,
  78
  79   // Memory instruction formats.
  80   MUBUF = 1 << 17,
  81   MTBUF = 1 << 18,
  82   SMRD = 1 << 19,
  83   MIMG = 1 << 20,
  84   VIMAGE = 1 << 21,
  85   VSAMPLE = 1 << 22,
  86   EXP = 1 << 23,
  87   FLAT = 1 << 24,
  88   DS = 1 << 25,
  89
  90   // Pseudo instruction formats.
  91   VGPRSpill = 1 << 26,
  92   SGPRSpill = 1 << 27,
  93
  94   // LDSDIR instruction format.
  95   LDSDIR = 1 << 28,
  96
  97   // VINTERP instruction format.
  98   VINTERP = 1 << 29,
  99
 100   // High bits - other information.
 101   VM_CNT = UINT64_C(1) << 32,
 102   EXP_CNT = UINT64_C(1) << 33,
 103   LGKM_CNT = UINT64_C(1) << 34,
 104
 105   WQM = UINT64_C(1) << 35,
 106   DisableWQM = UINT64_C(1) << 36,
 107   Gather4 = UINT64_C(1) << 37,
 108   SOPK_ZEXT = UINT64_C(1) << 38,
 109   SCALAR_STORE = UINT64_C(1) << 39,
 110   FIXED_SIZE = UINT64_C(1) << 40,
 111   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
 112   VOP3_OPSEL = UINT64_C(1) << 42,
 113   maybeAtomic = UINT64_C(1) << 43,
 114   renamedInGFX9 = UINT64_C(1) << 44,
 115
 116   // Is a clamp on FP type.
 117   FPClamp = UINT64_C(1) << 45,
 118
 119   // Is an integer clamp
 120   IntClamp = UINT64_C(1) << 46,
 121
 122   // Clamps lo component of register.
 123   ClampLo = UINT64_C(1) << 47,
 124
 125   // Clamps hi component of register.
 126   // ClampLo and ClampHi set for packed clamp.
 127   ClampHi = UINT64_C(1) << 48,
 128
 129   // Is a packed VOP3P instruction.
 130   IsPacked = UINT64_C(1) << 49,
 131
 132   // Is a D16 buffer instruction.
 133   D16Buf = UINT64_C(1) << 50,
 134
 135   // FLAT instruction accesses FLAT_GLBL segment.
 136   FlatGlobal = UINT64_C(1) << 51,
 137
 138   // Uses floating point double precision rounding mode
 139   FPDPRounding = UINT64_C(1) << 52,
 140
 141   // Instruction is FP atomic.
 142   FPAtomic = UINT64_C(1) << 53,
 143
 144   // Is a MFMA instruction.
 145   IsMAI = UINT64_C(1) << 54,
 146
 147   // Is a DOT instruction.
 148   IsDOT = UINT64_C(1) << 55,
 149
 150   // FLAT instruction accesses FLAT_SCRATCH segment.
 151   FlatScratch = UINT64_C(1) << 56,
 152
 153   // Atomic without return.
 154   IsAtomicNoRet = UINT64_C(1) << 57,
 155
 156   // Atomic with return.
 157   IsAtomicRet = UINT64_C(1) << 58,
 158
 159   // Is a WMMA instruction.
 160   IsWMMA = UINT64_C(1) << 59,
 161
 162   // Whether tied sources will be read.
 163   TiedSourceNotRead = UINT64_C(1) << 60,
 164
 165   // Is never uniform.
 166   IsNeverUniform = UINT64_C(1) << 61,
 167
 168   // ds_gws_* instructions.
 169   GWS = UINT64_C(1) << 62,
 170 };
 171
 172 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
 173 // The result is true if any of these tests are true.
 174 enum ClassFlags : unsigned {
 175   S_NAN = 1 << 0,        // Signaling NaN
 176   Q_NAN = 1 << 1,        // Quiet NaN
 177   N_INFINITY = 1 << 2,   // Negative infinity
 178   N_NORMAL = 1 << 3,     // Negative normal
 179   N_SUBNORMAL = 1 << 4,  // Negative subnormal
 180   N_ZERO = 1 << 5,       // Negative zero
 181   P_ZERO = 1 << 6,       // Positive zero
 182   P_SUBNORMAL = 1 << 7,  // Positive subnormal
 183   P_NORMAL = 1 << 8,     // Positive normal
 184   P_INFINITY = 1 << 9    // Positive infinity
 185 };
 186 }
 187
 188 namespace AMDGPU {
 189 enum OperandType : unsigned {
 190   /// Operands with register or 32-bit immediate
 191   OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
 192   OPERAND_REG_IMM_INT64,
 193   OPERAND_REG_IMM_INT16,
 194   OPERAND_REG_IMM_FP32,
 195   OPERAND_REG_IMM_FP64,
 196   OPERAND_REG_IMM_FP16,
 197   OPERAND_REG_IMM_FP16_DEFERRED,
 198   OPERAND_REG_IMM_FP32_DEFERRED,
 199   OPERAND_REG_IMM_V2FP16,
 200   OPERAND_REG_IMM_V2INT16,
 201   OPERAND_REG_IMM_V2INT32,
 202   OPERAND_REG_IMM_V2FP32,
 203
 204   /// Operands with register or inline constant
 205   OPERAND_REG_INLINE_C_INT16,
 206   OPERAND_REG_INLINE_C_INT32,
 207   OPERAND_REG_INLINE_C_INT64,
 208   OPERAND_REG_INLINE_C_FP16,
 209   OPERAND_REG_INLINE_C_FP32,
 210   OPERAND_REG_INLINE_C_FP64,
 211   OPERAND_REG_INLINE_C_V2INT16,
 212   OPERAND_REG_INLINE_C_V2FP16,
 213   OPERAND_REG_INLINE_C_V2INT32,
 214   OPERAND_REG_INLINE_C_V2FP32,
 215
 216   /// Operand with 32-bit immediate that uses the constant bus.
 217   OPERAND_KIMM32,
 218   OPERAND_KIMM16,
 219
 220   /// Operands with an AccVGPR register or inline constant
 221   OPERAND_REG_INLINE_AC_INT16,
 222   OPERAND_REG_INLINE_AC_INT32,
 223   OPERAND_REG_INLINE_AC_FP16,
 224   OPERAND_REG_INLINE_AC_FP32,
 225   OPERAND_REG_INLINE_AC_FP64,
 226   OPERAND_REG_INLINE_AC_V2INT16,
 227   OPERAND_REG_INLINE_AC_V2FP16,
 228   OPERAND_REG_INLINE_AC_V2INT32,
 229   OPERAND_REG_INLINE_AC_V2FP32,
 230
 231   // Operand for source modifiers for VOP instructions
 232   OPERAND_INPUT_MODS,
 233
 234   // Operand for SDWA instructions
 235   OPERAND_SDWA_VOPC_DST,
 236
 237   OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
 238   OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
 239
 240   OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
 241   OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
 242
 243   OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
 244   OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,
 245
 246   OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
 247   OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
 248
 249   OPERAND_KIMM_FIRST = OPERAND_KIMM32,
 250   OPERAND_KIMM_LAST = OPERAND_KIMM16
 251
 252 };
 253 }
 254
 255 // Input operand modifiers bit-masks
 256 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
 257 namespace SISrcMods {
 258   enum : unsigned {
 259    NONE = 0,
 260    NEG = 1 << 0,   // Floating-point negate modifier
 261    ABS = 1 << 1,   // Floating-point absolute modifier
 262    SEXT = 1 << 0,  // Integer sign-extend modifier
 263    NEG_HI = ABS,   // Floating-point negate high packed component modifier.
 264    OP_SEL_0 = 1 << 2,
 265    OP_SEL_1 = 1 << 3,
 266    DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
 267   };
 268 }
 269
 270 namespace SIOutMods {
 271   enum : unsigned {
 272     NONE = 0,
 273     MUL2 = 1,
 274     MUL4 = 2,
 275     DIV2 = 3
 276   };
 277 }
 278
 279 namespace AMDGPU {
 280 namespace VGPRIndexMode {
 281
 282 enum Id : unsigned { // id of symbolic names
 283   ID_SRC0 = 0,
 284   ID_SRC1,
 285   ID_SRC2,
 286   ID_DST,
 287
 288   ID_MIN = ID_SRC0,
 289   ID_MAX = ID_DST
 290 };
 291
 292 enum EncBits : unsigned {
 293   OFF = 0,
 294   SRC0_ENABLE = 1 << ID_SRC0,
 295   SRC1_ENABLE = 1 << ID_SRC1,
 296   SRC2_ENABLE = 1 << ID_SRC2,
 297   DST_ENABLE = 1 << ID_DST,
 298   ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
 299   UNDEF = 0xFFFF
 300 };
 301
 302 } // namespace VGPRIndexMode
 303 } // namespace AMDGPU
 304
 305 namespace AMDGPUAsmVariants {
 306   enum : unsigned {
 307     DEFAULT = 0,
 308     VOP3 = 1,
 309     SDWA = 2,
 310     SDWA9 = 3,
 311     DPP = 4,
 312     VOP3_DPP = 5
 313   };
 314 } // namespace AMDGPUAsmVariants
 315
 316 namespace AMDGPU {
 317 namespace EncValues { // Encoding values of enum9/8/7 operands
 318
 319 enum : unsigned {
 320   SGPR_MIN = 0,
 321   SGPR_MAX_SI = 101,
 322   SGPR_MAX_GFX10 = 105,
 323   TTMP_VI_MIN = 112,
 324   TTMP_VI_MAX = 123,
 325   TTMP_GFX9PLUS_MIN = 108,
 326   TTMP_GFX9PLUS_MAX = 123,
 327   INLINE_INTEGER_C_MIN = 128,
 328   INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
 329   INLINE_INTEGER_C_MAX = 208,
 330   INLINE_FLOATING_C_MIN = 240,
 331   INLINE_FLOATING_C_MAX = 248,
 332   LITERAL_CONST = 255,
 333   VGPR_MIN = 256,
 334   VGPR_MAX = 511,
 335   IS_VGPR = 256, // Indicates VGPR or AGPR
 336 };
 337
 338 } // namespace EncValues
 339
 340 // Register codes as defined in the TableGen's HWEncoding field.
 341 namespace HWEncoding {
 342 enum : unsigned {
 343   REG_IDX_MASK = 0xff,
 344   IS_VGPR_OR_AGPR = 1 << 8,
 345   IS_HI = 1 << 9, // High 16-bit register.
 346 };
 347 } // namespace HWEncoding
 348
 349 namespace CPol {
 350
 351 enum CPol {
 352   GLC = 1,
 353   SLC = 2,
 354   DLC = 4,
 355   SCC = 16,
 356   SC0 = GLC,
 357   SC1 = SCC,
 358   NT = SLC,
 359   ALL_pregfx12 = GLC | SLC | DLC | SCC,
 360   SWZ_pregfx12 = 8,
 361
 362   // Below are GFX12+ cache policy bits
 363
 364   // Temporal hint
 365   TH = 0x7,      // All TH bits
 366   TH_RT = 0,     // regular
 367   TH_NT = 1,     // non-temporal
 368   TH_HT = 2,     // high-temporal
 369   TH_LU = 3,     // last use
 370   TH_RT_WB = 3,  // regular (CU, SE), high-temporal with write-back (MALL)
 371   TH_NT_RT = 4,  // non-temporal (CU, SE), regular (MALL)
 372   TH_RT_NT = 5,  // regular (CU, SE), non-temporal (MALL)
 373   TH_NT_HT = 6,  // non-temporal (CU, SE), high-temporal (MALL)
 374   TH_NT_WB = 7,  // non-temporal (CU, SE), high-temporal with write-back (MALL)
 375   TH_BYPASS = 3, // only to be used with scope = 3
 376
 377   TH_RESERVED = 7, // unused value for load insts
 378
 379   // Bits of TH for atomics
 380   TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
 381   TH_ATOMIC_NT = SLC,     // Non-temporal vs regular
 382   TH_ATOMIC_CASCADE = 4,  // Cascading vs regular
 383
 384   // Scope
 385   SCOPE = 0x3 << 3, // All Scope bits
 386   SCOPE_CU = 0 << 3,
 387   SCOPE_SE = 1 << 3,
 388   SCOPE_DEV = 2 << 3,
 389   SCOPE_SYS = 3 << 3,
 390
 391   SWZ = 1 << 6, // Swizzle bit
 392
 393   ALL = TH | SCOPE,
 394
 395   // Helper bits
 396   TH_TYPE_LOAD = 1 << 7,    // TH_LOAD policy
 397   TH_TYPE_STORE = 1 << 8,   // TH_STORE policy
 398   TH_TYPE_ATOMIC = 1 << 9,  // TH_ATOMIC policy
 399   TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
 400 };
 401
 402 } // namespace CPol
 403
 404 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
 405
 406 enum Id { // Message ID, width(4) [3:0].
 407   ID_INTERRUPT = 1,
 408
 409   ID_GS_PreGFX11 = 2,      // replaced in GFX11
 410   ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
 411
 412   ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
 413   ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
 414
 415   ID_SAVEWAVE = 4,           // added in GFX8, removed in GFX11
 416   ID_STALL_WAVE_GEN = 5,     // added in GFX9, removed in GFX12
 417   ID_HALT_WAVES = 6,         // added in GFX9, removed in GFX12
 418   ID_ORDERED_PS_DONE = 7,    // added in GFX9, removed in GFX11
 419   ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
 420   ID_GS_ALLOC_REQ = 9,       // added in GFX9
 421   ID_GET_DOORBELL = 10,      // added in GFX9, removed in GFX11
 422   ID_GET_DDID = 11,          // added in GFX10, removed in GFX11
 423   ID_SYSMSG = 15,
 424
 425   ID_RTN_GET_DOORBELL = 128,
 426   ID_RTN_GET_DDID = 129,
 427   ID_RTN_GET_TMA = 130,
 428   ID_RTN_GET_REALTIME = 131,
 429   ID_RTN_SAVE_WAVE = 132,
 430   ID_RTN_GET_TBA = 133,
 431   ID_RTN_GET_SE_AID_ID = 134,
 432
 433   ID_MASK_PreGFX11_ = 0xF,
 434   ID_MASK_GFX11Plus_ = 0xFF
 435 };
 436
 437 enum Op { // Both GS and SYS operation IDs.
 438   OP_UNKNOWN_ = -1,
 439   OP_SHIFT_ = 4,
 440   OP_NONE_ = 0,
 441   // Bits used for operation encoding
 442   OP_WIDTH_ = 3,
 443   OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
 444   // GS operations are encoded in bits 5:4
 445   OP_GS_NOP = 0,
 446   OP_GS_CUT = 1,
 447   OP_GS_EMIT = 2,
 448   OP_GS_EMIT_CUT = 3,
 449   OP_GS_LAST_,
 450   OP_GS_FIRST_ = OP_GS_NOP,
 451   // SYS operations are encoded in bits 6:4
 452   OP_SYS_ECC_ERR_INTERRUPT = 1,
 453   OP_SYS_REG_RD = 2,
 454   OP_SYS_HOST_TRAP_ACK = 3,
 455   OP_SYS_TTRACE_PC = 4,
 456   OP_SYS_LAST_,
 457   OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
 458 };
 459
 460 enum StreamId : unsigned { // Stream ID, (2) [9:8].
 461   STREAM_ID_NONE_ = 0,
 462   STREAM_ID_DEFAULT_ = 0,
 463   STREAM_ID_LAST_ = 4,
 464   STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
 465   STREAM_ID_SHIFT_ = 8,
 466   STREAM_ID_WIDTH_=  2,
 467   STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
 468 };
 469
 470 } // namespace SendMsg
 471
 472 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
 473
 474 enum Id { // HwRegCode, (6) [5:0]
 475   ID_MODE = 1,
 476   ID_STATUS = 2,
 477   ID_TRAPSTS = 3,
 478   ID_HW_ID = 4,
 479   ID_GPR_ALLOC = 5,
 480   ID_LDS_ALLOC = 6,
 481   ID_IB_STS = 7,
 482   ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
 483   ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
 484   ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
 485   ID_MEM_BASES = 15,
 486   ID_TBA_LO = 16,
 487   ID_TBA_HI = 17,
 488   ID_TMA_LO = 18,
 489   ID_TMA_HI = 19,
 490   ID_FLAT_SCR_LO = 20,
 491   ID_FLAT_SCR_HI = 21,
 492   ID_XNACK_MASK = 22,
 493   ID_HW_ID1 = 23,
 494   ID_HW_ID2 = 24,
 495   ID_POPS_PACKER = 25,
 496   ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
 497   ID_SHADER_CYCLES = 29,
 498   ID_SHADER_CYCLES_HI = 30,
 499   ID_DVGPR_ALLOC_LO = 31,
 500   ID_DVGPR_ALLOC_HI = 32,
 501
 502   // Register numbers reused in GFX11
 503   ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
 504   ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
 505
 506   // Register numbers reused in GFX12+
 507   ID_STATE_PRIV = 4,
 508   ID_PERF_SNAPSHOT_DATA1 = 15,
 509   ID_PERF_SNAPSHOT_DATA2 = 16,
 510   ID_EXCP_FLAG_PRIV = 17,
 511   ID_EXCP_FLAG_USER = 18,
 512   ID_TRAP_CTRL = 19,
 513
 514   // GFX940 specific registers
 515   ID_XCC_ID = 20,
 516   ID_SQ_PERF_SNAPSHOT_DATA = 21,
 517   ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
 518   ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
 519   ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
 520
 521   ID_SHIFT_ = 0,
 522   ID_WIDTH_ = 6,
 523   ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
 524 };
 525
 526 enum Offset : unsigned { // Offset, (5) [10:6]
 527   OFFSET_DEFAULT_ = 0,
 528   OFFSET_SHIFT_ = 6,
 529   OFFSET_WIDTH_ = 5,
 530   OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
 531
 532   OFFSET_MEM_VIOL = 8,
 533 };
 534
 535 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
 536   WIDTH_M1_DEFAULT_ = 31,
 537   WIDTH_M1_SHIFT_ = 11,
 538   WIDTH_M1_WIDTH_ = 5,
 539   WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
 540 };
 541
 542 // Some values from WidthMinusOne mapped into Width domain.
 543 enum Width : unsigned {
 544   WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1,
 545 };
 546
 547 enum ModeRegisterMasks : uint32_t {
 548   FP_ROUND_MASK = 0xf << 0,  // Bits 0..3
 549   FP_DENORM_MASK = 0xf << 4, // Bits 4..7
 550   DX10_CLAMP_MASK = 1 << 8,
 551   IEEE_MODE_MASK = 1 << 9,
 552   LOD_CLAMP_MASK = 1 << 10,
 553   DEBUG_MASK = 1 << 11,
 554
 555   // EXCP_EN fields.
 556   EXCP_EN_INVALID_MASK = 1 << 12,
 557   EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
 558   EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
 559   EXCP_EN_OVERFLOW_MASK = 1 << 15,
 560   EXCP_EN_UNDERFLOW_MASK = 1 << 16,
 561   EXCP_EN_INEXACT_MASK = 1 << 17,
 562   EXCP_EN_INT_DIV0_MASK = 1 << 18,
 563
 564   GPR_IDX_EN_MASK = 1 << 27,
 565   VSKIP_MASK = 1 << 28,
 566   CSP_MASK = 0x7u << 29 // Bits 29..31
 567 };
 568
 569 } // namespace Hwreg
 570
 571 namespace MTBUFFormat {
 572
 573 enum DataFormat : int64_t {
 574   DFMT_INVALID = 0,
 575   DFMT_8,
 576   DFMT_16,
 577   DFMT_8_8,
 578   DFMT_32,
 579   DFMT_16_16,
 580   DFMT_10_11_11,
 581   DFMT_11_11_10,
 582   DFMT_10_10_10_2,
 583   DFMT_2_10_10_10,
 584   DFMT_8_8_8_8,
 585   DFMT_32_32,
 586   DFMT_16_16_16_16,
 587   DFMT_32_32_32,
 588   DFMT_32_32_32_32,
 589   DFMT_RESERVED_15,
 590
 591   DFMT_MIN = DFMT_INVALID,
 592   DFMT_MAX = DFMT_RESERVED_15,
 593
 594   DFMT_UNDEF = -1,
 595   DFMT_DEFAULT = DFMT_8,
 596
 597   DFMT_SHIFT = 0,
 598   DFMT_MASK = 0xF
 599 };
 600
 601 enum NumFormat : int64_t {
 602   NFMT_UNORM = 0,
 603   NFMT_SNORM,
 604   NFMT_USCALED,
 605   NFMT_SSCALED,
 606   NFMT_UINT,
 607   NFMT_SINT,
 608   NFMT_RESERVED_6,                    // VI and GFX9
 609   NFMT_SNORM_OGL = NFMT_RESERVED_6,   // SI and CI only
 610   NFMT_FLOAT,
 611
 612   NFMT_MIN = NFMT_UNORM,
 613   NFMT_MAX = NFMT_FLOAT,
 614
 615   NFMT_UNDEF = -1,
 616   NFMT_DEFAULT = NFMT_UNORM,
 617
 618   NFMT_SHIFT = 4,
 619   NFMT_MASK = 7
 620 };
 621
 622 enum MergedFormat : int64_t {
 623   DFMT_NFMT_UNDEF = -1,
 624   DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
 625                       ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
 626
 627
 628   DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
 629
 630   DFMT_NFMT_MAX = DFMT_NFMT_MASK
 631 };
 632
 633 enum UnifiedFormatCommon : int64_t {
 634   UFMT_MAX = 127,
 635   UFMT_UNDEF = -1,
 636   UFMT_DEFAULT = 1
 637 };
 638
 639 } // namespace MTBUFFormat
 640
 641 namespace UfmtGFX10 {
 642 enum UnifiedFormat : int64_t {
 643   UFMT_INVALID = 0,
 644
 645   UFMT_8_UNORM,
 646   UFMT_8_SNORM,
 647   UFMT_8_USCALED,
 648   UFMT_8_SSCALED,
 649   UFMT_8_UINT,
 650   UFMT_8_SINT,
 651
 652   UFMT_16_UNORM,
 653   UFMT_16_SNORM,
 654   UFMT_16_USCALED,
 655   UFMT_16_SSCALED,
 656   UFMT_16_UINT,
 657   UFMT_16_SINT,
 658   UFMT_16_FLOAT,
 659
 660   UFMT_8_8_UNORM,
 661   UFMT_8_8_SNORM,
 662   UFMT_8_8_USCALED,
 663   UFMT_8_8_SSCALED,
 664   UFMT_8_8_UINT,
 665   UFMT_8_8_SINT,
 666
 667   UFMT_32_UINT,
 668   UFMT_32_SINT,
 669   UFMT_32_FLOAT,
 670
 671   UFMT_16_16_UNORM,
 672   UFMT_16_16_SNORM,
 673   UFMT_16_16_USCALED,
 674   UFMT_16_16_SSCALED,
 675   UFMT_16_16_UINT,
 676   UFMT_16_16_SINT,
 677   UFMT_16_16_FLOAT,
 678
 679   UFMT_10_11_11_UNORM,
 680   UFMT_10_11_11_SNORM,
 681   UFMT_10_11_11_USCALED,
 682   UFMT_10_11_11_SSCALED,
 683   UFMT_10_11_11_UINT,
 684   UFMT_10_11_11_SINT,
 685   UFMT_10_11_11_FLOAT,
 686
 687   UFMT_11_11_10_UNORM,
 688   UFMT_11_11_10_SNORM,
 689   UFMT_11_11_10_USCALED,
 690   UFMT_11_11_10_SSCALED,
 691   UFMT_11_11_10_UINT,
 692   UFMT_11_11_10_SINT,
 693   UFMT_11_11_10_FLOAT,
 694
 695   UFMT_10_10_10_2_UNORM,
 696   UFMT_10_10_10_2_SNORM,
 697   UFMT_10_10_10_2_USCALED,
 698   UFMT_10_10_10_2_SSCALED,
 699   UFMT_10_10_10_2_UINT,
 700   UFMT_10_10_10_2_SINT,
 701
 702   UFMT_2_10_10_10_UNORM,
 703   UFMT_2_10_10_10_SNORM,
 704   UFMT_2_10_10_10_USCALED,
 705   UFMT_2_10_10_10_SSCALED,
 706   UFMT_2_10_10_10_UINT,
 707   UFMT_2_10_10_10_SINT,
 708
 709   UFMT_8_8_8_8_UNORM,
 710   UFMT_8_8_8_8_SNORM,
 711   UFMT_8_8_8_8_USCALED,
 712   UFMT_8_8_8_8_SSCALED,
 713   UFMT_8_8_8_8_UINT,
 714   UFMT_8_8_8_8_SINT,
 715
 716   UFMT_32_32_UINT,
 717   UFMT_32_32_SINT,
 718   UFMT_32_32_FLOAT,
 719
 720   UFMT_16_16_16_16_UNORM,
 721   UFMT_16_16_16_16_SNORM,
 722   UFMT_16_16_16_16_USCALED,
 723   UFMT_16_16_16_16_SSCALED,
 724   UFMT_16_16_16_16_UINT,
 725   UFMT_16_16_16_16_SINT,
 726   UFMT_16_16_16_16_FLOAT,
 727
 728   UFMT_32_32_32_UINT,
 729   UFMT_32_32_32_SINT,
 730   UFMT_32_32_32_FLOAT,
 731   UFMT_32_32_32_32_UINT,
 732   UFMT_32_32_32_32_SINT,
 733   UFMT_32_32_32_32_FLOAT,
 734
 735   UFMT_FIRST = UFMT_INVALID,
 736   UFMT_LAST = UFMT_32_32_32_32_FLOAT,
 737 };
 738
 739 } // namespace UfmtGFX10
 740
 741 namespace UfmtGFX11 {
 742 enum UnifiedFormat : int64_t {
 743   UFMT_INVALID = 0,
 744
 745   UFMT_8_UNORM,
 746   UFMT_8_SNORM,
 747   UFMT_8_USCALED,
 748   UFMT_8_SSCALED,
 749   UFMT_8_UINT,
 750   UFMT_8_SINT,
 751
 752   UFMT_16_UNORM,
 753   UFMT_16_SNORM,
 754   UFMT_16_USCALED,
 755   UFMT_16_SSCALED,
 756   UFMT_16_UINT,
 757   UFMT_16_SINT,
 758   UFMT_16_FLOAT,
 759
 760   UFMT_8_8_UNORM,
 761   UFMT_8_8_SNORM,
 762   UFMT_8_8_USCALED,
 763   UFMT_8_8_SSCALED,
 764   UFMT_8_8_UINT,
 765   UFMT_8_8_SINT,
 766
 767   UFMT_32_UINT,
 768   UFMT_32_SINT,
 769   UFMT_32_FLOAT,
 770
 771   UFMT_16_16_UNORM,
 772   UFMT_16_16_SNORM,
 773   UFMT_16_16_USCALED,
 774   UFMT_16_16_SSCALED,
 775   UFMT_16_16_UINT,
 776   UFMT_16_16_SINT,
 777   UFMT_16_16_FLOAT,
 778
 779   UFMT_10_11_11_FLOAT,
 780
 781   UFMT_11_11_10_FLOAT,
 782
 783   UFMT_10_10_10_2_UNORM,
 784   UFMT_10_10_10_2_SNORM,
 785   UFMT_10_10_10_2_UINT,
 786   UFMT_10_10_10_2_SINT,
 787
 788   UFMT_2_10_10_10_UNORM,
 789   UFMT_2_10_10_10_SNORM,
 790   UFMT_2_10_10_10_USCALED,
 791   UFMT_2_10_10_10_SSCALED,
 792   UFMT_2_10_10_10_UINT,
 793   UFMT_2_10_10_10_SINT,
 794
 795   UFMT_8_8_8_8_UNORM,
 796   UFMT_8_8_8_8_SNORM,
 797   UFMT_8_8_8_8_USCALED,
 798   UFMT_8_8_8_8_SSCALED,
 799   UFMT_8_8_8_8_UINT,
 800   UFMT_8_8_8_8_SINT,
 801
 802   UFMT_32_32_UINT,
 803   UFMT_32_32_SINT,
 804   UFMT_32_32_FLOAT,
 805
 806   UFMT_16_16_16_16_UNORM,
 807   UFMT_16_16_16_16_SNORM,
 808   UFMT_16_16_16_16_USCALED,
 809   UFMT_16_16_16_16_SSCALED,
 810   UFMT_16_16_16_16_UINT,
 811   UFMT_16_16_16_16_SINT,
 812   UFMT_16_16_16_16_FLOAT,
 813
 814   UFMT_32_32_32_UINT,
 815   UFMT_32_32_32_SINT,
 816   UFMT_32_32_32_FLOAT,
 817   UFMT_32_32_32_32_UINT,
 818   UFMT_32_32_32_32_SINT,
 819   UFMT_32_32_32_32_FLOAT,
 820
 821   UFMT_FIRST = UFMT_INVALID,
 822   UFMT_LAST = UFMT_32_32_32_32_FLOAT,
 823 };
 824
 825 } // namespace UfmtGFX11
 826
 827 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
 828
 829 enum Id : unsigned { // id of symbolic names
 830   ID_QUAD_PERM = 0,
 831   ID_BITMASK_PERM,
 832   ID_SWAP,
 833   ID_REVERSE,
 834   ID_BROADCAST
 835 };
 836
 837 enum EncBits : unsigned {
 838
 839   // swizzle mode encodings
 840
 841   QUAD_PERM_ENC         = 0x8000,
 842   QUAD_PERM_ENC_MASK    = 0xFF00,
 843
 844   BITMASK_PERM_ENC      = 0x0000,
 845   BITMASK_PERM_ENC_MASK = 0x8000,
 846
 847   // QUAD_PERM encodings
 848
 849   LANE_MASK             = 0x3,
 850   LANE_MAX              = LANE_MASK,
 851   LANE_SHIFT            = 2,
 852   LANE_NUM              = 4,
 853
 854   // BITMASK_PERM encodings
 855
 856   BITMASK_MASK          = 0x1F,
 857   BITMASK_MAX           = BITMASK_MASK,
 858   BITMASK_WIDTH         = 5,
 859
 860   BITMASK_AND_SHIFT     = 0,
 861   BITMASK_OR_SHIFT      = 5,
 862   BITMASK_XOR_SHIFT     = 10
 863 };
 864
 865 } // namespace Swizzle
 866
 867 namespace SDWA {
 868
 869 enum SdwaSel : unsigned {
 870   BYTE_0 = 0,
 871   BYTE_1 = 1,
 872   BYTE_2 = 2,
 873   BYTE_3 = 3,
 874   WORD_0 = 4,
 875   WORD_1 = 5,
 876   DWORD = 6,
 877 };
 878
 879 enum DstUnused : unsigned {
 880   UNUSED_PAD = 0,
 881   UNUSED_SEXT = 1,
 882   UNUSED_PRESERVE = 2,
 883 };
 884
 885 enum SDWA9EncValues : unsigned {
 886   SRC_SGPR_MASK = 0x100,
 887   SRC_VGPR_MASK = 0xFF,
 888   VOPC_DST_VCC_MASK = 0x80,
 889   VOPC_DST_SGPR_MASK = 0x7F,
 890
 891   SRC_VGPR_MIN = 0,
 892   SRC_VGPR_MAX = 255,
 893   SRC_SGPR_MIN = 256,
 894   SRC_SGPR_MAX_SI = 357,
 895   SRC_SGPR_MAX_GFX10 = 361,
 896   SRC_TTMP_MIN = 364,
 897   SRC_TTMP_MAX = 379,
 898 };
 899
 900 } // namespace SDWA
 901
 902 namespace DPP {
 903
 904 // clang-format off
 905 enum DppCtrl : unsigned {
 906   QUAD_PERM_FIRST   = 0,
 907   QUAD_PERM_ID      = 0xE4, // identity permutation
 908   QUAD_PERM_LAST    = 0xFF,
 909   DPP_UNUSED1       = 0x100,
 910   ROW_SHL0          = 0x100,
 911   ROW_SHL_FIRST     = 0x101,
 912   ROW_SHL_LAST      = 0x10F,
 913   DPP_UNUSED2       = 0x110,
 914   ROW_SHR0          = 0x110,
 915   ROW_SHR_FIRST     = 0x111,
 916   ROW_SHR_LAST      = 0x11F,
 917   DPP_UNUSED3       = 0x120,
 918   ROW_ROR0          = 0x120,
 919   ROW_ROR_FIRST     = 0x121,
 920   ROW_ROR_LAST      = 0x12F,
 921   WAVE_SHL1         = 0x130,
 922   DPP_UNUSED4_FIRST = 0x131,
 923   DPP_UNUSED4_LAST  = 0x133,
 924   WAVE_ROL1         = 0x134,
 925   DPP_UNUSED5_FIRST = 0x135,
 926   DPP_UNUSED5_LAST  = 0x137,
 927   WAVE_SHR1         = 0x138,
 928   DPP_UNUSED6_FIRST = 0x139,
 929   DPP_UNUSED6_LAST  = 0x13B,
 930   WAVE_ROR1         = 0x13C,
 931   DPP_UNUSED7_FIRST = 0x13D,
 932   DPP_UNUSED7_LAST  = 0x13F,
 933   ROW_MIRROR        = 0x140,
 934   ROW_HALF_MIRROR   = 0x141,
 935   BCAST15           = 0x142,
 936   BCAST31           = 0x143,
 937   DPP_UNUSED8_FIRST = 0x144,
 938   DPP_UNUSED8_LAST  = 0x14F,
 939   ROW_NEWBCAST_FIRST= 0x150,
 940   ROW_NEWBCAST_LAST = 0x15F,
 941   ROW_SHARE0        = 0x150,
 942   ROW_SHARE_FIRST   = 0x150,
 943   ROW_SHARE_LAST    = 0x15F,
 944   ROW_XMASK0        = 0x160,
 945   ROW_XMASK_FIRST   = 0x160,
 946   ROW_XMASK_LAST    = 0x16F,
 947   DPP_LAST          = ROW_XMASK_LAST
 948 };
 949 // clang-format on
 950
 951 enum DppFiMode {
 952   DPP_FI_0  = 0,
 953   DPP_FI_1  = 1,
 954   DPP8_FI_0 = 0xE9,
 955   DPP8_FI_1 = 0xEA,
 956 };
 957
 958 } // namespace DPP
 959
 960 namespace Exp {
 961
 962 enum Target : unsigned {
 963   ET_MRT0 = 0,
 964   ET_MRT7 = 7,
 965   ET_MRTZ = 8,
 966   ET_NULL = 9,             // Pre-GFX11
 967   ET_POS0 = 12,
 968   ET_POS3 = 15,
 969   ET_POS4 = 16,            // GFX10+
 970   ET_POS_LAST = ET_POS4,   // Highest pos used on any subtarget
 971   ET_PRIM = 20,            // GFX10+
 972   ET_DUAL_SRC_BLEND0 = 21, // GFX11+
 973   ET_DUAL_SRC_BLEND1 = 22, // GFX11+
 974   ET_PARAM0 = 32,          // Pre-GFX11
 975   ET_PARAM31 = 63,         // Pre-GFX11
 976
 977   ET_NULL_MAX_IDX = 0,
 978   ET_MRTZ_MAX_IDX = 0,
 979   ET_PRIM_MAX_IDX = 0,
 980   ET_MRT_MAX_IDX = 7,
 981   ET_POS_MAX_IDX = 4,
 982   ET_DUAL_SRC_BLEND_MAX_IDX = 1,
 983   ET_PARAM_MAX_IDX = 31,
 984
 985   ET_INVALID = 255,
 986 };
 987
 988 } // namespace Exp
 989
 990 namespace VOP3PEncoding {
 991
 992 enum OpSel : uint64_t {
 993   OP_SEL_HI_0 = UINT64_C(1) << 59,
 994   OP_SEL_HI_1 = UINT64_C(1) << 60,
 995   OP_SEL_HI_2 = UINT64_C(1) << 14,
 996 };
 997
 998 } // namespace VOP3PEncoding
 999
1000 namespace ImplicitArg {
1001 // Implicit kernel argument offset for code object version 5.
1002 enum Offset_COV5 : unsigned {
1003   HOSTCALL_PTR_OFFSET = 80,
1004   MULTIGRID_SYNC_ARG_OFFSET = 88,
1005   HEAP_PTR_OFFSET = 96,
1006
1007   DEFAULT_QUEUE_OFFSET = 104,
1008   COMPLETION_ACTION_OFFSET = 112,
1009
1010   PRIVATE_BASE_OFFSET = 192,
1011   SHARED_BASE_OFFSET = 196,
1012   QUEUE_PTR_OFFSET = 200,
1013 };
1014
1015 } // namespace ImplicitArg
1016
1017 namespace VirtRegFlag {
1018 // Virtual register flags used for various target specific handlings during
1019 // codegen.
1020 enum Register_Flag : uint8_t {
1021   // Register operand in a whole-wave mode operation.
1022   WWM_REG = 1 << 0,
1023 };
1024
1025 } // namespace VirtRegFlag
1026
1027 } // namespace AMDGPU
1028
1029 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
1030 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
1031 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
1032 #define   S_00B028_MEM_ORDERED(x)                                     (((x) & 0x1) << 25)
1033 #define   G_00B028_MEM_ORDERED(x)                                     (((x) >> 25) & 0x1)
1034 #define   C_00B028_MEM_ORDERED                                        0xFDFFFFFF
1035
1036 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
1037 #define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
1038 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
1039 #define   S_00B128_MEM_ORDERED(x)                                     (((x) & 0x1) << 27)
1040 #define   G_00B128_MEM_ORDERED(x)                                     (((x) >> 27) & 0x1)
1041 #define   C_00B128_MEM_ORDERED                                        0xF7FFFFFF
1042
1043 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
1044 #define   S_00B228_WGP_MODE(x)                                        (((x) & 0x1) << 27)
1045 #define   G_00B228_WGP_MODE(x)                                        (((x) >> 27) & 0x1)
1046 #define   C_00B228_WGP_MODE                                           0xF7FFFFFF
1047 #define   S_00B228_MEM_ORDERED(x)                                     (((x) & 0x1) << 25)
1048 #define   G_00B228_MEM_ORDERED(x)                                     (((x) >> 25) & 0x1)
1049 #define   C_00B228_MEM_ORDERED                                        0xFDFFFFFF
1050
1051 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
1052 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
1053 #define   S_00B428_WGP_MODE(x)                                        (((x) & 0x1) << 26)
1054 #define   G_00B428_WGP_MODE(x)                                        (((x) >> 26) & 0x1)
1055 #define   C_00B428_WGP_MODE                                           0xFBFFFFFF
1056 #define   S_00B428_MEM_ORDERED(x)                                     (((x) & 0x1) << 24)
1057 #define   G_00B428_MEM_ORDERED(x)                                     (((x) >> 24) & 0x1)
1058 #define   C_00B428_MEM_ORDERED                                        0xFEFFFFFF
1059
1060 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
1061
1062 #define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
1063 #define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
1064 #define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
1065 #define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
1066 #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
1067 #define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
1068 #define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
1069 #define   S_00B84C_TRAP_HANDLER(x)                                    (((x) & 0x1) << 6)
1070 #define   G_00B84C_TRAP_HANDLER(x)                                    (((x) >> 6) & 0x1)
1071 #define   C_00B84C_TRAP_HANDLER                                       0xFFFFFFBF
1072 #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
1073 #define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
1074 #define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
1075 #define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
1076 #define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
1077 #define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
1078 #define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
1079 #define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
1080 #define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
1081 #define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
1082 #define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
1083 #define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
1084 #define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
1085 #define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
1086 #define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
1087 /* CIK */
1088 #define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
1089 #define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
1090 #define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
1091 /*     */
1092 #define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
1093 #define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
1094 #define   C_00B84C_LDS_SIZE                                           0xFF007FFF
1095 #define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
1096 #define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
1097 #define   C_00B84C_EXCP_EN
1098
1099 #define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
1100 #define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
1101
1102 #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
1103 #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
1104 #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
1105 #define   C_00B848_VGPRS                                              0xFFFFFFC0
1106 #define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
1107 #define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
1108 #define   C_00B848_SGPRS                                              0xFFFFFC3F
1109 #define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
1110 #define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
1111 #define   C_00B848_PRIORITY                                           0xFFFFF3FF
1112 #define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
1113 #define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
1114 #define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
1115 #define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
1116 #define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
1117 #define   C_00B848_PRIV                                               0xFFEFFFFF
1118 #define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
1119 #define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
1120 #define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
1121 #define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
1122 #define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
1123 #define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
1124 #define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
1125 #define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
1126 #define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
1127 #define   S_00B848_WGP_MODE(x)                                        (((x) & 0x1) << 29)
1128 #define   G_00B848_WGP_MODE(x)                                        (((x) >> 29) & 0x1)
1129 #define   C_00B848_WGP_MODE                                           0xDFFFFFFF
1130 #define   S_00B848_MEM_ORDERED(x)                                     (((x) & 0x1) << 30)
1131 #define   G_00B848_MEM_ORDERED(x)                                     (((x) >> 30) & 0x1)
1132 #define   C_00B848_MEM_ORDERED                                        0xBFFFFFFF
1133 #define   S_00B848_FWD_PROGRESS(x)                                    (((x) & 0x1) << 31)
1134 #define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
1135 #define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
1136
1137
1138 // Helpers for setting FLOAT_MODE
1139 #define FP_ROUND_ROUND_TO_NEAREST 0
1140 #define FP_ROUND_ROUND_TO_INF 1
1141 #define FP_ROUND_ROUND_TO_NEGINF 2
1142 #define FP_ROUND_ROUND_TO_ZERO 3
1143
1144 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1145 // precision.
1146 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1147 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1148
1149 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1150 #define FP_DENORM_FLUSH_OUT 1
1151 #define FP_DENORM_FLUSH_IN 2
1152 #define FP_DENORM_FLUSH_NONE 3
1153
1154
1155 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1156 // precision.
1157 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1158 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1159
1160 #define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
1161 #define   S_00B860_WAVESIZE_PreGFX11(x)                               (((x) & 0x1FFF) << 12)
1162 #define   S_00B860_WAVESIZE_GFX11Plus(x)                              (((x) & 0x7FFF) << 12)
1163
1164 #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
1165 #define   S_0286E8_WAVESIZE_PreGFX11(x)                               (((x) & 0x1FFF) << 12)
1166 #define   S_0286E8_WAVESIZE_GFX11Plus(x)                              (((x) & 0x7FFF) << 12)
1167
1168 #define R_028B54_VGT_SHADER_STAGES_EN                                 0x028B54
1169 #define   S_028B54_HS_W32_EN(x)                                       (((x) & 0x1) << 21)
1170 #define   S_028B54_GS_W32_EN(x)                                       (((x) & 0x1) << 22)
1171 #define   S_028B54_VS_W32_EN(x)                                       (((x) & 0x1) << 23)
1172 #define R_0286D8_SPI_PS_IN_CONTROL                                    0x0286D8
1173 #define   S_0286D8_PS_W32_EN(x)                                       (((x) & 0x1) << 15)
1174 #define R_00B800_COMPUTE_DISPATCH_INITIATOR                           0x00B800
1175 #define   S_00B800_CS_W32_EN(x)                                       (((x) & 0x1) << 15)
1176
1177 #define R_SPILLED_SGPRS         0x4
1178 #define R_SPILLED_VGPRS         0x8
1179 } // End namespace llvm
1180
1181 #endif