clang/test/CodeGen/arm-vector-arguments.c

   1 // REQUIRES: arm-registered-target
   2 // RUN: %clang_cc1 -triple thumbv7-apple-darwin9 \
   3 // RUN:   -target-abi apcs-gnu \
   4 // RUN:   -target-cpu cortex-a8 \
   5 // RUN:   -mfloat-abi soft \
   6 // RUN:   -target-feature +soft-float-abi \
   7 // RUN:   -ffreestanding \
   8 // RUN:   -emit-llvm -w -o - %s | FileCheck %s
   9
  10 #include <arm_neon.h>
  11
  12 // CHECK: define{{.*}} void @f0(ptr dead_on_unwind noalias writable sret(%struct.int8x16x2_t) align 16 %agg.result, <16 x i8> noundef %{{.*}}, <16 x i8> noundef %{{.*}})
  13 int8x16x2_t f0(int8x16_t a0, int8x16_t a1) {
  14   return vzipq_s8(a0, a1);
  15 }
  16
  17 // Test direct vector passing.
  18
  19 typedef float T_float32x2 __attribute__ ((__vector_size__ (8)));
  20 typedef float T_float32x4 __attribute__ ((__vector_size__ (16)));
  21 typedef float T_float32x8 __attribute__ ((__vector_size__ (32)));
  22 typedef float T_float32x16 __attribute__ ((__vector_size__ (64)));
  23
  24 // CHECK: define{{.*}} <2 x float> @f1_0(<2 x float> noundef %{{.*}})
  25 T_float32x2 f1_0(T_float32x2 a0) { return a0; }
  26 // CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> noundef %{{.*}})
  27 T_float32x4 f1_1(T_float32x4 a0) { return a0; }
  28 // CHECK: define{{.*}} void @f1_2(ptr dead_on_unwind noalias writable sret(<8 x float>) align 32 %{{.*}}, <8 x float> noundef %{{.*}})
  29 T_float32x8 f1_2(T_float32x8 a0) { return a0; }
  30 // CHECK: define{{.*}} void @f1_3(ptr dead_on_unwind noalias writable sret(<16 x float>) align 64 %{{.*}}, <16 x float> noundef %{{.*}})
  31 T_float32x16 f1_3(T_float32x16 a0) { return a0; }