[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedIn...
[llvm-project.git] / clang / test / CodeGen / attr-mode-enums.c
blob772f126ff36d0fe621d10695734b1908986d7e48
1 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
3 // Test checks that 'mode' attribute is handled correctly with enums, i. e. code
4 // 1. "typedef enum { A } __attribute__((mode(HI))) T;" is accepted,
5 // 2. "enum X __attribute__((mode(QI))) var;" forms a complete integer type.
7 int main(void) {
8 // CHECK: [[X1:%.+]] = alloca i8
9 enum { A1, B1 } __attribute__((mode(QI))) x1 = A1;
11 // CHECK: [[X2:%.+]] = alloca i16
12 enum { A2, B2 } x2 __attribute__((mode(HI))) = B2;
14 // CHECK: [[X3:%.+]] = alloca i32
15 typedef enum { A3, B3 } __attribute__((mode(SI))) T3;
16 T3 x3 = A3;
18 // CHECK: [[X4:%.+]] = alloca i64
19 typedef enum { A4, B4 } T4 __attribute__((mode(DI)));
20 T4 x4 = B4;
22 // CHECK: [[X5:%.+]] = alloca i8
23 typedef enum __attribute__((mode(QI))) { A5, B5 } T5;
24 T5 x5 = A5;
26 // CHECK: [[X6:%.+]] = alloca i8
27 typedef enum X __attribute__((mode(QI))) T6;
28 T6 x6;
30 // CHECK: [[X7:%.+]] = alloca i128
31 enum { A7, B7 } __attribute__((mode(TI))) x7 = A7;
33 // CHECK: [[X8:%.+]] = alloca i8
34 enum __attribute__((mode(QI))) { A8, B8 } x8 = B8;
36 // CHECK: store i8 0, ptr [[X1]]
37 // CHECK: store i16 1, ptr [[X2]]
38 // CHECK: store i32 0, ptr [[X3]]
39 // CHECK: store i64 1, ptr [[X4]]
40 // CHECK: store i8 0, ptr [[X5]]
41 // CHECK: store i128 0, ptr [[X7]]
42 // CHECK: store i8 1, ptr [[X8]]
44 return x1 + x2 + x3 + x4 + x5 + x6 + x7 + x8;