[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedIn...
[llvm-project.git] / clang / test / CodeGen / neon-immediate-ubsan.c
blob9e914995373ffe1a4d303ea250e59d97471115e9
1 // RUN: %clang_cc1 -triple armv7s-linux-gnu -target-abi apcs-gnu -emit-llvm -o - %s \
2 // RUN: -target-feature +neon -target-cpu cortex-a8 \
3 // RUN: -fsanitize=signed-integer-overflow \
4 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARMV7
6 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -emit-llvm -o - %s \
7 // RUN: -target-feature +neon -target-cpu cortex-a53 \
8 // RUN: -fsanitize=signed-integer-overflow \
9 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
11 // REQUIRES: aarch64-registered-target || arm-registered-target
13 // Verify we emit constants for "immediate" builtin arguments.
14 // Emitting a scalar expression can make the immediate be generated as
15 // overflow intrinsics, if the overflow sanitizer is enabled.
17 // PR23517
19 #include <arm_neon.h>
21 int32x2_t test_vqrshrn_n_s64(int64x2_t a) {
22 // CHECK-LABEL: @test_vqrshrn_n_s64
23 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> {{.*}}, i32 1)
24 // CHECK-ARMV7: call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> {{.*}}, <2 x i64> splat (i64 -1))
25 return vqrshrn_n_s64(a, 0 + 1);