clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -O1 -disable-llvm-passes -emit-llvm %s -o - -triple=x86_64-linux-gnu | FileCheck %s
   3
   4 extern volatile int i;
   5
   6 // CHECK-LABEL: @_Z8OneCaseLv(
   7 // CHECK-NEXT:  entry:
   8 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2:![0-9]+]]
   9 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  10 // CHECK-NEXT:    i32 1, label [[SW_EPILOG]]
  11 // CHECK-NEXT:    ], !prof !6
  12 // CHECK:       sw.epilog:
  13 // CHECK-NEXT:    ret void
  14 //
  15 void OneCaseL() {
  16   switch (i) {
  17     [[likely]] case 1: break;
  18   }
  19 }
  20
  21 // CHECK-LABEL: @_Z8OneCaseUv(
  22 // CHECK-NEXT:  entry:
  23 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  24 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  25 // CHECK-NEXT:    i32 1, label [[SW_BB:%.*]]
  26 // CHECK-NEXT:    ], !prof !7
  27 // CHECK:       sw.bb:
  28 // CHECK-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  29 // CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  30 // CHECK-NEXT:    store volatile i32 [[INC]], ptr @i, align 4, !tbaa [[TBAA2]]
  31 // CHECK-NEXT:    br label [[SW_EPILOG]]
  32 // CHECK:       sw.epilog:
  33 // CHECK-NEXT:    ret void
  34 //
  35 void OneCaseU() {
  36   switch (i) {
  37     [[unlikely]] case 1: ++i; break;
  38   }
  39 }
  40
  41 // CHECK-LABEL: @_Z10TwoCasesLNv(
  42 // CHECK-NEXT:  entry:
  43 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  44 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  45 // CHECK-NEXT:    i32 1, label [[SW_EPILOG]]
  46 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
  47 // CHECK-NEXT:    ], !prof !8
  48 // CHECK:       sw.epilog:
  49 // CHECK-NEXT:    ret void
  50 //
  51 void TwoCasesLN() {
  52   switch (i) {
  53     [[likely]] case 1: break;
  54     case 2: break;
  55   }
  56 }
  57
  58 // CHECK-LABEL: @_Z10TwoCasesUNv(
  59 // CHECK-NEXT:  entry:
  60 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  61 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  62 // CHECK-NEXT:    i32 1, label [[SW_EPILOG]]
  63 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
  64 // CHECK-NEXT:    ], !prof !9
  65 // CHECK:       sw.epilog:
  66 // CHECK-NEXT:    ret void
  67 //
  68 void TwoCasesUN() {
  69   switch (i) {
  70     [[unlikely]] case 1: break;
  71     case 2: break;
  72   }
  73 }
  74
  75 // CHECK-LABEL: @_Z10TwoCasesLUv(
  76 // CHECK-NEXT:  entry:
  77 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  78 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  79 // CHECK-NEXT:    i32 1, label [[SW_EPILOG]]
  80 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
  81 // CHECK-NEXT:    ], !prof !10
  82 // CHECK:       sw.epilog:
  83 // CHECK-NEXT:    ret void
  84 //
  85 void TwoCasesLU() {
  86   switch (i) {
  87     [[likely]] case 1: break;
  88     [[unlikely]] case 2: break;
  89   }
  90 }
  91
  92 // CHECK-LABEL: @_Z20CasesFallthroughNNLNv(
  93 // CHECK-NEXT:  entry:
  94 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
  95 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
  96 // CHECK-NEXT:    i32 1, label [[SW_BB:%.*]]
  97 // CHECK-NEXT:    i32 2, label [[SW_BB]]
  98 // CHECK-NEXT:    i32 3, label [[SW_BB1:%.*]]
  99 // CHECK-NEXT:    i32 4, label [[SW_BB1]]
 100 // CHECK-NEXT:    ], !prof !11
 101 // CHECK:       sw.bb:
 102 // CHECK-NEXT:    br label [[SW_BB1]]
 103 // CHECK:       sw.bb1:
 104 // CHECK-NEXT:    br label [[SW_EPILOG]]
 105 // CHECK:       sw.epilog:
 106 // CHECK-NEXT:    ret void
 107 //
 108 void CasesFallthroughNNLN() {
 109   switch (i) {
 110     case 1:
 111     case 2:
 112     [[likely]] case 3:
 113     case 4: break;
 114   }
 115 }
 116
 117 // CHECK-LABEL: @_Z20CasesFallthroughNNUNv(
 118 // CHECK-NEXT:  entry:
 119 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 120 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
 121 // CHECK-NEXT:    i32 1, label [[SW_BB:%.*]]
 122 // CHECK-NEXT:    i32 2, label [[SW_BB]]
 123 // CHECK-NEXT:    i32 3, label [[SW_BB1:%.*]]
 124 // CHECK-NEXT:    i32 4, label [[SW_BB1]]
 125 // CHECK-NEXT:    ], !prof !12
 126 // CHECK:       sw.bb:
 127 // CHECK-NEXT:    br label [[SW_BB1]]
 128 // CHECK:       sw.bb1:
 129 // CHECK-NEXT:    br label [[SW_EPILOG]]
 130 // CHECK:       sw.epilog:
 131 // CHECK-NEXT:    ret void
 132 //
 133 void CasesFallthroughNNUN() {
 134   switch (i) {
 135     case 1:
 136     case 2:
 137     [[unlikely]] case 3:
 138     case 4: break;
 139   }
 140 }
 141
 142 // CHECK-LABEL: @_Z28CasesFallthroughRangeSmallLNv(
 143 // CHECK-NEXT:  entry:
 144 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 145 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
 146 // CHECK-NEXT:    i32 1, label [[SW_BB:%.*]]
 147 // CHECK-NEXT:    i32 2, label [[SW_BB]]
 148 // CHECK-NEXT:    i32 3, label [[SW_BB]]
 149 // CHECK-NEXT:    i32 4, label [[SW_BB]]
 150 // CHECK-NEXT:    i32 5, label [[SW_BB]]
 151 // CHECK-NEXT:    i32 102, label [[SW_BB1:%.*]]
 152 // CHECK-NEXT:    i32 103, label [[SW_BB2:%.*]]
 153 // CHECK-NEXT:    i32 104, label [[SW_BB2]]
 154 // CHECK-NEXT:    ], !prof !13
 155 // CHECK:       sw.bb:
 156 // CHECK-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 157 // CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
 158 // CHECK-NEXT:    store volatile i32 [[INC]], ptr @i, align 4, !tbaa [[TBAA2]]
 159 // CHECK-NEXT:    br label [[SW_BB1]]
 160 // CHECK:       sw.bb1:
 161 // CHECK-NEXT:    br label [[SW_BB2]]
 162 // CHECK:       sw.bb2:
 163 // CHECK-NEXT:    br label [[SW_EPILOG]]
 164 // CHECK:       sw.epilog:
 165 // CHECK-NEXT:    ret void
 166 //
 167 void CasesFallthroughRangeSmallLN() {
 168   switch (i) {
 169     case 1 ... 5: ++i;
 170     case 102:
 171     [[likely]] case 103:
 172     case 104: break;
 173   }
 174 }
 175
 176 // CHECK-LABEL: @_Z28CasesFallthroughRangeSmallUNv(
 177 // CHECK-NEXT:  entry:
 178 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 179 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_EPILOG:%.*]] [
 180 // CHECK-NEXT:    i32 1, label [[SW_BB:%.*]]
 181 // CHECK-NEXT:    i32 2, label [[SW_BB]]
 182 // CHECK-NEXT:    i32 3, label [[SW_BB]]
 183 // CHECK-NEXT:    i32 4, label [[SW_BB]]
 184 // CHECK-NEXT:    i32 5, label [[SW_BB]]
 185 // CHECK-NEXT:    i32 102, label [[SW_BB1:%.*]]
 186 // CHECK-NEXT:    i32 103, label [[SW_BB2:%.*]]
 187 // CHECK-NEXT:    i32 104, label [[SW_BB2]]
 188 // CHECK-NEXT:    ], !prof !14
 189 // CHECK:       sw.bb:
 190 // CHECK-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 191 // CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
 192 // CHECK-NEXT:    store volatile i32 [[INC]], ptr @i, align 4, !tbaa [[TBAA2]]
 193 // CHECK-NEXT:    br label [[SW_BB1]]
 194 // CHECK:       sw.bb1:
 195 // CHECK-NEXT:    br label [[SW_BB2]]
 196 // CHECK:       sw.bb2:
 197 // CHECK-NEXT:    br label [[SW_EPILOG]]
 198 // CHECK:       sw.epilog:
 199 // CHECK-NEXT:    ret void
 200 //
 201 void CasesFallthroughRangeSmallUN() {
 202   switch (i) {
 203     case 1 ... 5: ++i;
 204     case 102:
 205     [[unlikely]] case 103:
 206     case 104: break;
 207   }
 208 }
 209
 210 // CHECK-LABEL: @_Z29CasesFallthroughRangeLargeLLNv(
 211 // CHECK-NEXT:  entry:
 212 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 213 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_CASERANGE:%.*]] [
 214 // CHECK-NEXT:    i32 1003, label [[SW_BB1:%.*]]
 215 // CHECK-NEXT:    i32 104, label [[SW_BB1]]
 216 // CHECK-NEXT:    ], !prof !8
 217 // CHECK:       sw.bb:
 218 // CHECK-NEXT:    br label [[SW_BB1]]
 219 // CHECK:       sw.bb1:
 220 // CHECK-NEXT:    br label [[SW_EPILOG:%.*]]
 221 // CHECK:       sw.caserange:
 222 // CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[TMP0]], 0
 223 // CHECK-NEXT:    [[INBOUNDS:%.*]] = icmp ule i32 [[TMP1]], 64
 224 // CHECK-NEXT:    [[INBOUNDS_EXPVAL:%.*]] = call i1 @llvm.expect.i1(i1 [[INBOUNDS]], i1 true)
 225 // CHECK-NEXT:    br i1 [[INBOUNDS_EXPVAL]], label [[SW_BB:%.*]], label [[SW_EPILOG]]
 226 // CHECK:       sw.epilog:
 227 // CHECK-NEXT:    ret void
 228 //
 229 void CasesFallthroughRangeLargeLLN() {
 230   switch (i) {
 231     [[likely]] case 0 ... 64:
 232     [[likely]] case 1003:
 233     case 104: break;
 234   }
 235 }
 236
 237 // CHECK-LABEL: @_Z29CasesFallthroughRangeLargeUUNv(
 238 // CHECK-NEXT:  entry:
 239 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 240 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_CASERANGE:%.*]] [
 241 // CHECK-NEXT:    i32 1003, label [[SW_BB1:%.*]]
 242 // CHECK-NEXT:    i32 104, label [[SW_BB1]]
 243 // CHECK-NEXT:    ], !prof !9
 244 // CHECK:       sw.bb:
 245 // CHECK-NEXT:    br label [[SW_BB1]]
 246 // CHECK:       sw.bb1:
 247 // CHECK-NEXT:    br label [[SW_EPILOG:%.*]]
 248 // CHECK:       sw.caserange:
 249 // CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[TMP0]], 0
 250 // CHECK-NEXT:    [[INBOUNDS:%.*]] = icmp ule i32 [[TMP1]], 64
 251 // CHECK-NEXT:    [[INBOUNDS_EXPVAL:%.*]] = call i1 @llvm.expect.i1(i1 [[INBOUNDS]], i1 false)
 252 // CHECK-NEXT:    br i1 [[INBOUNDS_EXPVAL]], label [[SW_BB:%.*]], label [[SW_EPILOG]]
 253 // CHECK:       sw.epilog:
 254 // CHECK-NEXT:    ret void
 255 //
 256 void CasesFallthroughRangeLargeUUN() {
 257   switch (i) {
 258     [[unlikely]] case 0 ... 64:
 259     [[unlikely]] case 1003:
 260     case 104: break;
 261   }
 262 }
 263
 264 // CHECK-LABEL: @_Z15OneCaseDefaultLv(
 265 // CHECK-NEXT:  entry:
 266 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 267 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
 268 // CHECK-NEXT:    i32 1, label [[SW_EPILOG:%.*]]
 269 // CHECK-NEXT:    ], !prof !15
 270 // CHECK:       sw.default:
 271 // CHECK-NEXT:    br label [[SW_EPILOG]]
 272 // CHECK:       sw.epilog:
 273 // CHECK-NEXT:    ret void
 274 //
 275 void OneCaseDefaultL() {
 276   switch (i) {
 277     case 1: break;
 278     [[likely]] default: break;
 279   }
 280 }
 281
 282 // CHECK-LABEL: @_Z15OneCaseDefaultUv(
 283 // CHECK-NEXT:  entry:
 284 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 285 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
 286 // CHECK-NEXT:    i32 1, label [[SW_EPILOG:%.*]]
 287 // CHECK-NEXT:    ], !prof !16
 288 // CHECK:       sw.default:
 289 // CHECK-NEXT:    br label [[SW_EPILOG]]
 290 // CHECK:       sw.epilog:
 291 // CHECK-NEXT:    ret void
 292 //
 293 void OneCaseDefaultU() {
 294   switch (i) {
 295     case 1: break;
 296     [[unlikely]] default: break;
 297   }
 298 }
 299
 300 // CHECK-LABEL: @_Z18TwoCasesDefaultLNLv(
 301 // CHECK-NEXT:  entry:
 302 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 303 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
 304 // CHECK-NEXT:    i32 1, label [[SW_EPILOG:%.*]]
 305 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
 306 // CHECK-NEXT:    ], !prof !17
 307 // CHECK:       sw.default:
 308 // CHECK-NEXT:    br label [[SW_EPILOG]]
 309 // CHECK:       sw.epilog:
 310 // CHECK-NEXT:    ret void
 311 //
 312 void TwoCasesDefaultLNL() {
 313   switch (i) {
 314     [[likely]] case 1: break;
 315     case 2: break;
 316     [[likely]] default: break;
 317   }
 318 }
 319
 320 // CHECK-LABEL: @_Z18TwoCasesDefaultLNNv(
 321 // CHECK-NEXT:  entry:
 322 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 323 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
 324 // CHECK-NEXT:    i32 1, label [[SW_EPILOG:%.*]]
 325 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
 326 // CHECK-NEXT:    ], !prof !8
 327 // CHECK:       sw.default:
 328 // CHECK-NEXT:    br label [[SW_EPILOG]]
 329 // CHECK:       sw.epilog:
 330 // CHECK-NEXT:    ret void
 331 //
 332 void TwoCasesDefaultLNN() {
 333   switch (i) {
 334     [[likely]] case 1: break;
 335     case 2: break;
 336     default: break;
 337   }
 338 }
 339
 340 // CHECK-LABEL: @_Z18TwoCasesDefaultLNUv(
 341 // CHECK-NEXT:  entry:
 342 // CHECK-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @i, align 4, !tbaa [[TBAA2]]
 343 // CHECK-NEXT:    switch i32 [[TMP0]], label [[SW_DEFAULT:%.*]] [
 344 // CHECK-NEXT:    i32 1, label [[SW_EPILOG:%.*]]
 345 // CHECK-NEXT:    i32 2, label [[SW_EPILOG]]
 346 // CHECK-NEXT:    ], !prof !18
 347 // CHECK:       sw.default:
 348 // CHECK-NEXT:    br label [[SW_EPILOG]]
 349 // CHECK:       sw.epilog:
 350 // CHECK-NEXT:    ret void
 351 //
 352 void TwoCasesDefaultLNU() {
 353   switch (i) {
 354     [[likely]] case 1: break;
 355     case 2: break;
 356     [[unlikely]] default: break;
 357   }
 358 }