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[OpenACC] Treat 'delete' as a valid clause during parsing in C++ mode
[llvm-project.git] / clang / test / OpenMP / teams_distribute_parallel_for_firstprivate_codegen.cpp
blobd742b0a85af4276a6bc74d7eb11e16d0c2060651
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
30 St() : a(0), b(0) {}
31 St(const St &st) : a(st.a + st.b), b(0) {}
32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
41 S(T a) : f(a + g) {}
42 S() : f(g) {}
43 S(const S &s, St t = St()) : f(s.f + t.a) {}
44 operator T() { return T(); }
45 ~S() {}
46 };
47
48
49 template <typename T>
50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for firstprivate(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global and bound tid vars
80 // skip loop vars
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global and bound tid vars, and prev lb and ub vars
86 // skip loop vars
87
88 // use of private vars
89 [&]() {
90 g = 2;
91 g1 = 2;
92 sivar = 4;
93
94 }();
95 }
96 }();
97 return 0;
98 #else
99 #pragma omp target
100 #pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar)
101 for (int i = 0; i < 2; ++i) {
102 vec[i] = t_var;
103 s_arr[i] = var;
104 sivar += i;
105 }
106 return tmain<int>();
107 #endif
108 }
109
110
111
112
113
114 // Skip global and bound tid vars
115 // Skip temp vars for loop
116
117 // param copy
118
119 // T_VAR and SIVAR
120
121 // preparation vars
122
123 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
124
125 // firstprivate(s_arr)
126
127 // firstprivate(var)
128
129
130 // Skip global and bound tid vars, and prev lb ub vars
131 // Skip temp vars for loop
132
133 // param copy
134
135 // T_VAR and SIVAR
136
137 // preparation vars
138
139 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
140
141 // firstprivate(s_arr)
142
143 // firstprivate(var)
144
145
146
147
148
149
150 // Skip global and bound tid vars
151 // Skip temp vars for loop
152
153 // param copy
154
155 // T_VAR and preparation variables
156
157 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
158
159 // firstprivate(s_arr)
160
161 // firstprivate(var)
162
163
164 // Skip global and bound tid vars
165 // Skip temp vars for loop
166
167 // param copy
168
169 // T_VAR and preparation variables
170
171 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
172
173 // firstprivate(s_arr)
174
175 // firstprivate(var)
176
177
178 #endif
179 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
180 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
181 // CHECK1-NEXT: entry:
182 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
183 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
184 // CHECK1-NEXT: ret void
185 //
186 //
187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
188 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
189 // CHECK1-NEXT: entry:
190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
191 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
192 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
194 // CHECK1-NEXT: ret void
195 //
196 //
197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
198 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
199 // CHECK1-NEXT: entry:
200 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
201 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
202 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
203 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
204 // CHECK1-NEXT: ret void
205 //
206 //
207 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
208 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
209 // CHECK1-NEXT: entry:
210 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
211 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
214 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
215 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
216 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
217 // CHECK1-NEXT: ret void
218 //
219 //
220 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
221 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
222 // CHECK1-NEXT: entry:
223 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
224 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
225 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
226 // CHECK1-NEXT: ret void
227 //
228 //
229 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
230 // CHECK1-SAME: () #[[ATTR0]] {
231 // CHECK1-NEXT: entry:
232 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
233 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
234 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
235 // CHECK1-NEXT: ret void
236 //
237 //
238 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
239 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
240 // CHECK1-NEXT: entry:
241 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
242 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
243 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
244 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
245 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
246 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
247 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
248 // CHECK1-NEXT: ret void
249 //
250 //
251 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
252 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
253 // CHECK1-NEXT: entry:
254 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
255 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
256 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
257 // CHECK1: arraydestroy.body:
258 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
259 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
260 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
261 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
262 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
263 // CHECK1: arraydestroy.done1:
264 // CHECK1-NEXT: ret void
265 //
266 //
267 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
268 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
269 // CHECK1-NEXT: entry:
270 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
271 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
272 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
273 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
274 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
275 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
276 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
277 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
278 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
279 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
280 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
281 // CHECK1-NEXT: ret void
282 //
283 //
284 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
285 // CHECK1-SAME: () #[[ATTR0]] {
286 // CHECK1-NEXT: entry:
287 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
288 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
289 // CHECK1-NEXT: ret void
290 //
291 //
292 // CHECK1-LABEL: define {{[^@]+}}@main
293 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
294 // CHECK1-NEXT: entry:
295 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
296 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
297 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
298 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
299 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
300 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
301 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
303 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
304 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4
305 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
306 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
307 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
308 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
309 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
310 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
311 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8
312 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
313 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8
314 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
315 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
316 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
317 // CHECK1-NEXT: store ptr @vec, ptr [[TMP7]], align 8
318 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
319 // CHECK1-NEXT: store ptr @vec, ptr [[TMP8]], align 8
320 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
321 // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8
322 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
323 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8
324 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
325 // CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8
326 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
327 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
328 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
329 // CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8
330 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
331 // CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8
332 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
333 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8
334 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
335 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8
336 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
337 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8
338 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
339 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
340 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
341 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
342 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
343 // CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4
344 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
345 // CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4
346 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
347 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8
348 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
349 // CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8
350 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
351 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8
352 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
353 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8
354 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
355 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8
356 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
357 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8
358 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
359 // CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8
360 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
361 // CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8
362 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
363 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
364 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
365 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
366 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
367 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4
368 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, ptr [[KERNEL_ARGS]])
369 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
370 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
371 // CHECK1: omp_offload.failed:
372 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]
373 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
374 // CHECK1: omp_offload.cont:
375 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
376 // CHECK1-NEXT: ret i32 [[CALL]]
377 //
378 //
379 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
380 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
381 // CHECK1-NEXT: entry:
382 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
383 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
384 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
385 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
386 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
387 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
388 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
389 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
390 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
391 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
392 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
393 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
394 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
395 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
396 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
397 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
398 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
399 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
400 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
401 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
402 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
403 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])
404 // CHECK1-NEXT: ret void
405 //
406 //
407 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined
408 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
409 // CHECK1-NEXT: entry:
410 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
411 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
412 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
413 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
414 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
415 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
416 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
417 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
418 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
419 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
420 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
421 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
422 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
423 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
424 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
425 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
426 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
427 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
428 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
429 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
430 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
431 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
432 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
433 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
434 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
435 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
436 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
437 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
438 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
439 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
440 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
441 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
442 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
443 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
444 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
445 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)
446 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
447 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
448 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
449 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
450 // CHECK1: omp.arraycpy.body:
451 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
452 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
453 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
454 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
455 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
456 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
457 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
458 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
459 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
460 // CHECK1: omp.arraycpy.done3:
461 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
462 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
463 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
464 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
465 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
466 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
467 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
468 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
469 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
470 // CHECK1: cond.true:
471 // CHECK1-NEXT: br label [[COND_END:%.*]]
472 // CHECK1: cond.false:
473 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
474 // CHECK1-NEXT: br label [[COND_END]]
475 // CHECK1: cond.end:
476 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
477 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
478 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
479 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
480 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
481 // CHECK1: omp.inner.for.cond:
482 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
483 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
484 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
485 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
486 // CHECK1: omp.inner.for.cond.cleanup:
487 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
488 // CHECK1: omp.inner.for.body:
489 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
490 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
491 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
492 // CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
493 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
494 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4
495 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
496 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
497 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4
498 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
499 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]])
500 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
501 // CHECK1: omp.inner.for.inc:
502 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
503 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
504 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
505 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
506 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
507 // CHECK1: omp.inner.for.end:
508 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
509 // CHECK1: omp.loop.exit:
510 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
511 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
512 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
513 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
514 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
515 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
516 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
517 // CHECK1: arraydestroy.body:
518 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
519 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
520 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
521 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
522 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
523 // CHECK1: arraydestroy.done8:
524 // CHECK1-NEXT: ret void
525 //
526 //
527 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
528 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
529 // CHECK1-NEXT: entry:
530 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
531 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
532 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
533 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
534 // CHECK1-NEXT: ret void
535 //
536 //
537 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
538 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
539 // CHECK1-NEXT: entry:
540 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
541 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
542 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
543 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
544 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
545 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
546 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
547 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
548 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
549 // CHECK1-NEXT: ret void
550 //
551 //
552 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
553 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
554 // CHECK1-NEXT: entry:
555 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
556 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
557 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
558 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
559 // CHECK1-NEXT: ret void
560 //
561 //
562 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined
563 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
564 // CHECK1-NEXT: entry:
565 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
566 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
567 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
568 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
569 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
570 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
571 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
572 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
573 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
574 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
575 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
576 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
577 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
578 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
579 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
580 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
581 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
582 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
583 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
584 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
585 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
586 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
587 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
588 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
589 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
590 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
591 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
592 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
593 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
594 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
595 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
596 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
597 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
598 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
599 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
600 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
601 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
602 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
603 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32
604 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
605 // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
606 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
607 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
608 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)
609 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
610 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
611 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
612 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
613 // CHECK1: omp.arraycpy.body:
614 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
615 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
616 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
617 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
618 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
619 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
620 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
621 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
622 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
623 // CHECK1: omp.arraycpy.done4:
624 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
625 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]])
626 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
627 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
628 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
629 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
630 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
631 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
632 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
633 // CHECK1: cond.true:
634 // CHECK1-NEXT: br label [[COND_END:%.*]]
635 // CHECK1: cond.false:
636 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
637 // CHECK1-NEXT: br label [[COND_END]]
638 // CHECK1: cond.end:
639 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
640 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
641 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
642 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
643 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
644 // CHECK1: omp.inner.for.cond:
645 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
646 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
647 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
648 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
649 // CHECK1: omp.inner.for.cond.cleanup:
650 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
651 // CHECK1: omp.inner.for.body:
652 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
653 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
654 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
655 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
656 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
657 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
658 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
659 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]
660 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
661 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
662 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64
663 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
664 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false)
665 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
666 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
667 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]
668 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4
669 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
670 // CHECK1: omp.body.continue:
671 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
672 // CHECK1: omp.inner.for.inc:
673 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
674 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1
675 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
676 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
677 // CHECK1: omp.inner.for.end:
678 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
679 // CHECK1: omp.loop.exit:
680 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
681 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
682 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])
683 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
684 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
685 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2
686 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
687 // CHECK1: arraydestroy.body:
688 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
689 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
690 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
691 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
692 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
693 // CHECK1: arraydestroy.done13:
694 // CHECK1-NEXT: ret void
695 //
696 //
697 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
698 // CHECK1-SAME: () #[[ATTR1]] comdat {
699 // CHECK1-NEXT: entry:
700 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
701 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
702 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
703 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
704 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
705 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8
706 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
707 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
708 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
709 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
710 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
711 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
712 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
713 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
714 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4
715 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
716 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)
717 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
718 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
719 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
720 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
721 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
722 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
723 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
724 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
725 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
726 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
727 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
728 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
729 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8
730 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
731 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8
732 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
733 // CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8
734 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
735 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8
736 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
737 // CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8
738 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
739 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
740 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
741 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8
742 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
743 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8
744 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
745 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
746 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
747 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8
748 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
749 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8
750 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
751 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
752 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
753 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
754 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
755 // CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4
756 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
757 // CHECK1-NEXT: store i32 4, ptr [[TMP21]], align 4
758 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
759 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8
760 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
761 // CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8
762 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
763 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 8
764 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
765 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8
766 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
767 // CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8
768 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
769 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8
770 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
771 // CHECK1-NEXT: store i64 2, ptr [[TMP28]], align 8
772 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
773 // CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8
774 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
775 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
776 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
777 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
778 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
779 // CHECK1-NEXT: store i32 0, ptr [[TMP32]], align 4
780 // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
781 // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
782 // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
783 // CHECK1: omp_offload.failed:
784 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]
785 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
786 // CHECK1: omp_offload.cont:
787 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
788 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
789 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
790 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
791 // CHECK1: arraydestroy.body:
792 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
793 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
794 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
795 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
796 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
797 // CHECK1: arraydestroy.done2:
798 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
799 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
800 // CHECK1-NEXT: ret i32 [[TMP36]]
801 //
802 //
803 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
804 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
805 // CHECK1-NEXT: entry:
806 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
807 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
808 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
809 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
810 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
811 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
812 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4
813 // CHECK1-NEXT: ret void
814 //
815 //
816 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
817 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
818 // CHECK1-NEXT: entry:
819 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
820 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
821 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
822 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
823 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
824 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
825 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
826 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
827 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
828 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
829 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
830 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
831 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
832 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
833 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
834 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4
835 // CHECK1-NEXT: ret void
836 //
837 //
838 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
839 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
840 // CHECK1-NEXT: entry:
841 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
842 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
843 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
844 // CHECK1-NEXT: ret void
845 //
846 //
847 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
848 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
849 // CHECK1-NEXT: entry:
850 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
851 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
852 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
853 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
854 // CHECK1-NEXT: ret void
855 //
856 //
857 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
858 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
859 // CHECK1-NEXT: entry:
860 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
861 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
862 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
863 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
864 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
865 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
866 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
867 // CHECK1-NEXT: ret void
868 //
869 //
870 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
871 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
872 // CHECK1-NEXT: entry:
873 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
874 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
875 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
876 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
877 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
878 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
879 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
880 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
881 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
882 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
883 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
884 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
885 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
886 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
887 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
888 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
889 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
890 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
891 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
892 // CHECK1-NEXT: ret void
893 //
894 //
895 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
896 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
897 // CHECK1-NEXT: entry:
898 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
899 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
900 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
901 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
902 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
903 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
904 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
905 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
906 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
907 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
908 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
909 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
910 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
911 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
912 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
913 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
914 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
915 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
916 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
917 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
918 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
919 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
920 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
921 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
922 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
923 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
924 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
925 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
926 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
927 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
928 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
929 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
930 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
931 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
932 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
933 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)
934 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
935 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
936 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
937 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
938 // CHECK1: omp.arraycpy.body:
939 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
940 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
941 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
942 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
943 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
944 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
945 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
946 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
947 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
948 // CHECK1: omp.arraycpy.done4:
949 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
950 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
951 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])
952 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
953 // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8
954 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
955 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
956 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
957 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
958 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
959 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
960 // CHECK1: cond.true:
961 // CHECK1-NEXT: br label [[COND_END:%.*]]
962 // CHECK1: cond.false:
963 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
964 // CHECK1-NEXT: br label [[COND_END]]
965 // CHECK1: cond.end:
966 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
967 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
968 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
969 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
970 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
971 // CHECK1: omp.inner.for.cond:
972 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
973 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
974 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
975 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
976 // CHECK1: omp.inner.for.cond.cleanup:
977 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
978 // CHECK1: omp.inner.for.body:
979 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
980 // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
981 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
982 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
983 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
984 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4
985 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
986 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8
987 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]])
988 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
989 // CHECK1: omp.inner.for.inc:
990 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
991 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
992 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
993 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
994 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
995 // CHECK1: omp.inner.for.end:
996 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
997 // CHECK1: omp.loop.exit:
998 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
999 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
1000 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
1001 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1002 // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
1003 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2
1004 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1005 // CHECK1: arraydestroy.body:
1006 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1007 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1008 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1009 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1010 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1011 // CHECK1: arraydestroy.done10:
1012 // CHECK1-NEXT: ret void
1013 //
1014 //
1015 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1016 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1017 // CHECK1-NEXT: entry:
1018 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1019 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1020 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1021 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1022 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1023 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1024 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1025 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1026 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
1027 // CHECK1-NEXT: ret void
1028 //
1029 //
1030 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
1031 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1032 // CHECK1-NEXT: entry:
1033 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1034 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1035 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1036 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1037 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
1038 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1039 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1040 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
1041 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1042 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1043 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1044 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1045 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1046 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1047 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1048 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1049 // CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1050 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1051 // CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1052 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4
1053 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
1054 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1055 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1056 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1057 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1058 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1059 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1060 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1061 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1062 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1063 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1064 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1065 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1066 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
1067 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1068 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
1069 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1070 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1071 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1072 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1073 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1074 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1075 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1076 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1077 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)
1078 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1079 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1080 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1081 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1082 // CHECK1: omp.arraycpy.body:
1083 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1084 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1085 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1086 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1087 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1088 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1089 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1090 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1091 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
1092 // CHECK1: omp.arraycpy.done5:
1093 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
1094 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]])
1095 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]])
1096 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]]
1097 // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8
1098 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1099 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1100 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1101 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1102 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1103 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1104 // CHECK1: cond.true:
1105 // CHECK1-NEXT: br label [[COND_END:%.*]]
1106 // CHECK1: cond.false:
1107 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1108 // CHECK1-NEXT: br label [[COND_END]]
1109 // CHECK1: cond.end:
1110 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1111 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1112 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1113 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1114 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1115 // CHECK1: omp.inner.for.cond:
1116 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1117 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1118 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1119 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1120 // CHECK1: omp.inner.for.cond.cleanup:
1121 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1122 // CHECK1: omp.inner.for.body:
1123 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1124 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
1125 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1126 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1127 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1128 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1129 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
1130 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1131 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4
1132 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8
1133 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
1134 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64
1135 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]]
1136 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false)
1137 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1138 // CHECK1: omp.body.continue:
1139 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1140 // CHECK1: omp.inner.for.inc:
1141 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1142 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
1143 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
1144 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1145 // CHECK1: omp.inner.for.end:
1146 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1147 // CHECK1: omp.loop.exit:
1148 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1149 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1150 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])
1151 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]]
1152 // CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1153 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2
1154 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1155 // CHECK1: arraydestroy.body:
1156 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1157 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1158 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1159 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
1160 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
1161 // CHECK1: arraydestroy.done14:
1162 // CHECK1-NEXT: ret void
1163 //
1164 //
1165 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1166 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1167 // CHECK1-NEXT: entry:
1168 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1169 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1170 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1171 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1172 // CHECK1-NEXT: ret void
1173 //
1174 //
1175 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1176 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1177 // CHECK1-NEXT: entry:
1178 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1179 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1180 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1181 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1182 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1183 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
1184 // CHECK1-NEXT: ret void
1185 //
1186 //
1187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1188 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1189 // CHECK1-NEXT: entry:
1190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1191 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1192 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1193 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1194 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1195 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1196 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1197 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1198 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1199 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
1200 // CHECK1-NEXT: ret void
1201 //
1202 //
1203 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1204 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1205 // CHECK1-NEXT: entry:
1206 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1207 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1208 // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1209 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1210 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1211 // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1212 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1214 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1215 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
1216 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
1217 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
1218 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1219 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1220 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
1221 // CHECK1-NEXT: ret void
1222 //
1223 //
1224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1225 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1226 // CHECK1-NEXT: entry:
1227 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1228 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1229 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1230 // CHECK1-NEXT: ret void
1231 //
1232 //
1233 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
1234 // CHECK1-SAME: () #[[ATTR0]] {
1235 // CHECK1-NEXT: entry:
1236 // CHECK1-NEXT: call void @__cxx_global_var_init()
1237 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
1238 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
1239 // CHECK1-NEXT: ret void
1240 //
1241 //
1242 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1243 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1244 // CHECK3-NEXT: entry:
1245 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1246 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1247 // CHECK3-NEXT: ret void
1248 //
1249 //
1250 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1251 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1252 // CHECK3-NEXT: entry:
1253 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1254 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1255 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1256 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1257 // CHECK3-NEXT: ret void
1258 //
1259 //
1260 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1261 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1262 // CHECK3-NEXT: entry:
1263 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1264 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1265 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1266 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1267 // CHECK3-NEXT: ret void
1268 //
1269 //
1270 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1271 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1272 // CHECK3-NEXT: entry:
1273 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1274 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1275 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1276 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1277 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1278 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1279 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4
1280 // CHECK3-NEXT: ret void
1281 //
1282 //
1283 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1284 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1285 // CHECK3-NEXT: entry:
1286 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1287 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1288 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1289 // CHECK3-NEXT: ret void
1290 //
1291 //
1292 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1293 // CHECK3-SAME: () #[[ATTR0]] {
1294 // CHECK3-NEXT: entry:
1295 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1296 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
1297 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1298 // CHECK3-NEXT: ret void
1299 //
1300 //
1301 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1302 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1303 // CHECK3-NEXT: entry:
1304 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1305 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1306 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1307 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
1308 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1309 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1310 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1311 // CHECK3-NEXT: ret void
1312 //
1313 //
1314 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1315 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1316 // CHECK3-NEXT: entry:
1317 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4
1318 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4
1319 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1320 // CHECK3: arraydestroy.body:
1321 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1322 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1323 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1324 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1325 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1326 // CHECK3: arraydestroy.done1:
1327 // CHECK3-NEXT: ret void
1328 //
1329 //
1330 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1331 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1332 // CHECK3-NEXT: entry:
1333 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1334 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1335 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1336 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
1337 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1338 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1339 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1340 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1341 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1342 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1343 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4
1344 // CHECK3-NEXT: ret void
1345 //
1346 //
1347 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1348 // CHECK3-SAME: () #[[ATTR0]] {
1349 // CHECK3-NEXT: entry:
1350 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1351 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1352 // CHECK3-NEXT: ret void
1353 //
1354 //
1355 // CHECK3-LABEL: define {{[^@]+}}@main
1356 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1357 // CHECK3-NEXT: entry:
1358 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1359 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1360 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1361 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1362 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1363 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1364 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1365 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1366 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
1367 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4
1368 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
1369 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1370 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1371 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
1372 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1373 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1374 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4
1375 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1376 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4
1377 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1378 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4
1379 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1380 // CHECK3-NEXT: store ptr @vec, ptr [[TMP7]], align 4
1381 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1382 // CHECK3-NEXT: store ptr @vec, ptr [[TMP8]], align 4
1383 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1384 // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4
1385 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1386 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 4
1387 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1388 // CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 4
1389 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1390 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
1391 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1392 // CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 4
1393 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1394 // CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 4
1395 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1396 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4
1397 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1398 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4
1399 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1400 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4
1401 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1402 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4
1403 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1404 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1405 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1406 // CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 4
1407 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1408 // CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 4
1409 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1410 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4
1411 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1412 // CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4
1413 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1414 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4
1415 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1416 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4
1417 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1418 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4
1419 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1420 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4
1421 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1422 // CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 8
1423 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1424 // CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8
1425 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1426 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1427 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1428 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
1429 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1430 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4
1431 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, ptr [[KERNEL_ARGS]])
1432 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1433 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1434 // CHECK3: omp_offload.failed:
1435 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]
1436 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1437 // CHECK3: omp_offload.cont:
1438 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1439 // CHECK3-NEXT: ret i32 [[CALL]]
1440 //
1441 //
1442 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
1443 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1444 // CHECK3-NEXT: entry:
1445 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1446 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1447 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1448 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1449 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1450 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1451 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1452 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1453 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1454 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1455 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1456 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1457 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1458 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1459 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1460 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1461 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1462 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1463 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
1464 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
1465 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1466 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])
1467 // CHECK3-NEXT: ret void
1468 //
1469 //
1470 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined
1471 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1472 // CHECK3-NEXT: entry:
1473 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1474 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1475 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1476 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1477 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1478 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1479 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1480 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1481 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1482 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1483 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1484 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1485 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1486 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
1487 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1488 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1489 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1490 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1491 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1492 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1493 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1494 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1495 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1496 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1497 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1498 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1499 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1500 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1501 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1502 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1503 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1504 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1505 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1506 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1507 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1508 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)
1509 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1510 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1511 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
1512 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1513 // CHECK3: omp.arraycpy.body:
1514 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1515 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1516 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1517 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1518 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1519 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1520 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1521 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
1522 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1523 // CHECK3: omp.arraycpy.done3:
1524 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1525 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
1526 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1527 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1528 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1529 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1530 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1531 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1532 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1533 // CHECK3: cond.true:
1534 // CHECK3-NEXT: br label [[COND_END:%.*]]
1535 // CHECK3: cond.false:
1536 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1537 // CHECK3-NEXT: br label [[COND_END]]
1538 // CHECK3: cond.end:
1539 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1540 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1541 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1542 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1543 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1544 // CHECK3: omp.inner.for.cond:
1545 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1546 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1547 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1548 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1549 // CHECK3: omp.inner.for.cond.cleanup:
1550 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1551 // CHECK3: omp.inner.for.body:
1552 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1553 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1554 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1555 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4
1556 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1557 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
1558 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4
1559 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1560 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]])
1561 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1562 // CHECK3: omp.inner.for.inc:
1563 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1564 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1565 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1566 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1567 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1568 // CHECK3: omp.inner.for.end:
1569 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1570 // CHECK3: omp.loop.exit:
1571 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1572 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1573 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
1574 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1575 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1576 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2
1577 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1578 // CHECK3: arraydestroy.body:
1579 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1580 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1581 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1582 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1583 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1584 // CHECK3: arraydestroy.done8:
1585 // CHECK3-NEXT: ret void
1586 //
1587 //
1588 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1589 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1590 // CHECK3-NEXT: entry:
1591 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1592 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1593 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1594 // CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
1595 // CHECK3-NEXT: ret void
1596 //
1597 //
1598 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1599 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1600 // CHECK3-NEXT: entry:
1601 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1602 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
1603 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
1604 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1605 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
1606 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
1607 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1608 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
1609 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
1610 // CHECK3-NEXT: ret void
1611 //
1612 //
1613 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1614 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1615 // CHECK3-NEXT: entry:
1616 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1617 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1618 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1619 // CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1620 // CHECK3-NEXT: ret void
1621 //
1622 //
1623 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined
1624 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
1625 // CHECK3-NEXT: entry:
1626 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1627 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1628 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1629 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1630 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1631 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1632 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1633 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1634 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1635 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1636 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1637 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1638 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1639 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1640 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1641 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
1642 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1643 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1644 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1645 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1646 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1647 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1648 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1649 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1650 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1651 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1652 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1653 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1654 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1655 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1656 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1657 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1658 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1659 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1660 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
1661 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1662 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1663 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
1664 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1665 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1666 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1667 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)
1668 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1669 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1670 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1671 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1672 // CHECK3: omp.arraycpy.body:
1673 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1674 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1675 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1676 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1677 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1678 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1679 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1680 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1681 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1682 // CHECK3: omp.arraycpy.done3:
1683 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1684 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
1685 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1686 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1687 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1688 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1689 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1690 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1691 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1692 // CHECK3: cond.true:
1693 // CHECK3-NEXT: br label [[COND_END:%.*]]
1694 // CHECK3: cond.false:
1695 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1696 // CHECK3-NEXT: br label [[COND_END]]
1697 // CHECK3: cond.end:
1698 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1699 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1700 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1701 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1702 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1703 // CHECK3: omp.inner.for.cond:
1704 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1705 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1706 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1707 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1708 // CHECK3: omp.inner.for.cond.cleanup:
1709 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1710 // CHECK3: omp.inner.for.body:
1711 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1712 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1713 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1714 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1715 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1716 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1717 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]]
1718 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
1719 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1720 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]]
1721 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false)
1722 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1723 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
1724 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]
1725 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4
1726 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1727 // CHECK3: omp.body.continue:
1728 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1729 // CHECK3: omp.inner.for.inc:
1730 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1731 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
1732 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
1733 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1734 // CHECK3: omp.inner.for.end:
1735 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1736 // CHECK3: omp.loop.exit:
1737 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1738 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1739 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])
1740 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1741 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1742 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2
1743 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1744 // CHECK3: arraydestroy.body:
1745 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1746 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1747 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1748 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1749 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1750 // CHECK3: arraydestroy.done11:
1751 // CHECK3-NEXT: ret void
1752 //
1753 //
1754 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1755 // CHECK3-SAME: () #[[ATTR1]] comdat {
1756 // CHECK3-NEXT: entry:
1757 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1758 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1759 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1760 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1761 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1762 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4
1763 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1764 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1765 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1766 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1767 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1768 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1769 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1770 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1771 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4
1772 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1773 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
1774 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
1775 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1776 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
1777 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1778 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
1779 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1780 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1781 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1782 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1783 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
1784 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1785 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1786 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4
1787 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1788 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4
1789 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1790 // CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4
1791 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1792 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 4
1793 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1794 // CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 4
1795 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1796 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4
1797 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1798 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4
1799 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1800 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4
1801 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1802 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4
1803 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1804 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 4
1805 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1806 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 4
1807 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1808 // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4
1809 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1810 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1811 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1812 // CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4
1813 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1814 // CHECK3-NEXT: store i32 4, ptr [[TMP21]], align 4
1815 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1816 // CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 4
1817 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1818 // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4
1819 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1820 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 4
1821 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1822 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 4
1823 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1824 // CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4
1825 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1826 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4
1827 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1828 // CHECK3-NEXT: store i64 2, ptr [[TMP28]], align 8
1829 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1830 // CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8
1831 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1832 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
1833 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1834 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1835 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1836 // CHECK3-NEXT: store i32 0, ptr [[TMP32]], align 4
1837 // CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
1838 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1839 // CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1840 // CHECK3: omp_offload.failed:
1841 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]
1842 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1843 // CHECK3: omp_offload.cont:
1844 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
1845 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1846 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1847 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1848 // CHECK3: arraydestroy.body:
1849 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1850 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1851 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1852 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1853 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1854 // CHECK3: arraydestroy.done2:
1855 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1856 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
1857 // CHECK3-NEXT: ret i32 [[TMP36]]
1858 //
1859 //
1860 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1861 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1862 // CHECK3-NEXT: entry:
1863 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1864 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1865 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1866 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
1867 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
1868 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
1869 // CHECK3-NEXT: store i32 0, ptr [[B]], align 4
1870 // CHECK3-NEXT: ret void
1871 //
1872 //
1873 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1874 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1875 // CHECK3-NEXT: entry:
1876 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1877 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
1878 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
1879 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1880 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
1881 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
1882 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1883 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1884 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
1885 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
1886 // CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4
1887 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
1888 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1889 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1890 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1891 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4
1892 // CHECK3-NEXT: ret void
1893 //
1894 //
1895 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1896 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1897 // CHECK3-NEXT: entry:
1898 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1899 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1900 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1901 // CHECK3-NEXT: ret void
1902 //
1903 //
1904 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1905 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1906 // CHECK3-NEXT: entry:
1907 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1908 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1909 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1910 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1911 // CHECK3-NEXT: ret void
1912 //
1913 //
1914 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1915 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1916 // CHECK3-NEXT: entry:
1917 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1918 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1919 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1920 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1921 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1922 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1923 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1924 // CHECK3-NEXT: ret void
1925 //
1926 //
1927 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1928 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1929 // CHECK3-NEXT: entry:
1930 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1931 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1932 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1933 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1934 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1935 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1936 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1937 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1938 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1939 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1940 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1941 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1942 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1943 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
1944 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1945 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1946 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1947 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1948 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
1949 // CHECK3-NEXT: ret void
1950 //
1951 //
1952 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
1953 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1954 // CHECK3-NEXT: entry:
1955 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1956 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1957 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1958 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1959 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1960 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1961 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1962 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1963 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1964 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1965 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1966 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1967 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1968 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1969 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
1970 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1971 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1972 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1973 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4
1974 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1975 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1976 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1977 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1978 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1979 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1980 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1981 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1982 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1983 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1984 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1985 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
1986 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1987 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1988 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1989 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1990 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
1991 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
1992 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1993 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
1994 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1995 // CHECK3: omp.arraycpy.body:
1996 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1997 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1998 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1999 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
2000 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2001 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2002 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2003 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
2004 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2005 // CHECK3: omp.arraycpy.done4:
2006 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
2007 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2008 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])
2009 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2010 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4
2011 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2012 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2013 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2014 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2015 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
2016 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2017 // CHECK3: cond.true:
2018 // CHECK3-NEXT: br label [[COND_END:%.*]]
2019 // CHECK3: cond.false:
2020 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2021 // CHECK3-NEXT: br label [[COND_END]]
2022 // CHECK3: cond.end:
2023 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2024 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2025 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2026 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2027 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2028 // CHECK3: omp.inner.for.cond:
2029 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2030 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2031 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2032 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2033 // CHECK3: omp.inner.for.cond.cleanup:
2034 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2035 // CHECK3: omp.inner.for.body:
2036 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2037 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2038 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
2039 // CHECK3-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4
2040 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2041 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4
2042 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]])
2043 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2044 // CHECK3: omp.inner.for.inc:
2045 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2046 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2047 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
2048 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2049 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2050 // CHECK3: omp.inner.for.end:
2051 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2052 // CHECK3: omp.loop.exit:
2053 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2054 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2055 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
2056 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2057 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2058 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2
2059 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2060 // CHECK3: arraydestroy.body:
2061 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2062 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2063 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2064 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2065 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2066 // CHECK3: arraydestroy.done10:
2067 // CHECK3-NEXT: ret void
2068 //
2069 //
2070 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2071 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2072 // CHECK3-NEXT: entry:
2073 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2074 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
2075 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
2076 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2077 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
2078 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
2079 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2080 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
2081 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
2082 // CHECK3-NEXT: ret void
2083 //
2084 //
2085 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
2086 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2087 // CHECK3-NEXT: entry:
2088 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2089 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2090 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2091 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2092 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
2093 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2094 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2095 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
2096 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2097 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2098 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2099 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2100 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2101 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2102 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2103 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
2104 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2105 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2106 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2107 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2108 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4
2109 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2110 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2111 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2112 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2113 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2114 // CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2115 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2116 // CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2117 // CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2118 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2119 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2120 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2121 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
2122 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2123 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
2124 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2125 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2126 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2127 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2128 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2129 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2130 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
2131 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2132 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2133 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
2134 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2135 // CHECK3: omp.arraycpy.body:
2136 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2137 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2138 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2139 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
2140 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2141 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2142 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2143 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
2144 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2145 // CHECK3: omp.arraycpy.done4:
2146 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
2147 // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2148 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]])
2149 // CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2150 // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4
2151 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2152 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2153 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2154 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2155 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2156 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2157 // CHECK3: cond.true:
2158 // CHECK3-NEXT: br label [[COND_END:%.*]]
2159 // CHECK3: cond.false:
2160 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2161 // CHECK3-NEXT: br label [[COND_END]]
2162 // CHECK3: cond.end:
2163 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2164 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2165 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2166 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2167 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2168 // CHECK3: omp.inner.for.cond:
2169 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2170 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2171 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2172 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2173 // CHECK3: omp.inner.for.cond.cleanup:
2174 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2175 // CHECK3: omp.inner.for.body:
2176 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2177 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2178 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2179 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2180 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
2181 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
2182 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]
2183 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4
2184 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4
2185 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
2186 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]
2187 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false)
2188 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2189 // CHECK3: omp.body.continue:
2190 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2191 // CHECK3: omp.inner.for.inc:
2192 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2193 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1
2194 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
2195 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2196 // CHECK3: omp.inner.for.end:
2197 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2198 // CHECK3: omp.loop.exit:
2199 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2200 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2201 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])
2202 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2203 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2204 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2
2205 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2206 // CHECK3: arraydestroy.body:
2207 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2208 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2209 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2210 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2211 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2212 // CHECK3: arraydestroy.done12:
2213 // CHECK3-NEXT: ret void
2214 //
2215 //
2216 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2217 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2218 // CHECK3-NEXT: entry:
2219 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2220 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2221 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2222 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2223 // CHECK3-NEXT: ret void
2224 //
2225 //
2226 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2227 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2228 // CHECK3-NEXT: entry:
2229 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2230 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2231 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2232 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2233 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2234 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
2235 // CHECK3-NEXT: ret void
2236 //
2237 //
2238 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2239 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2240 // CHECK3-NEXT: entry:
2241 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2242 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2243 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2244 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2245 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2246 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2247 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2248 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2249 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2250 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4
2251 // CHECK3-NEXT: ret void
2252 //
2253 //
2254 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2255 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2256 // CHECK3-NEXT: entry:
2257 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2258 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
2259 // CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
2260 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2261 // CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
2262 // CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
2263 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2264 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2265 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
2266 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
2267 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
2268 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
2269 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
2270 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2271 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4
2272 // CHECK3-NEXT: ret void
2273 //
2274 //
2275 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2276 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2277 // CHECK3-NEXT: entry:
2278 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2279 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2280 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2281 // CHECK3-NEXT: ret void
2282 //
2283 //
2284 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
2285 // CHECK3-SAME: () #[[ATTR0]] {
2286 // CHECK3-NEXT: entry:
2287 // CHECK3-NEXT: call void @__cxx_global_var_init()
2288 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
2289 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
2290 // CHECK3-NEXT: ret void
2291 //
2292 //
2293 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
2294 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2295 // CHECK9-NEXT: entry:
2296 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2297 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2298 // CHECK9-NEXT: ret void
2299 //
2300 //
2301 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2302 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2303 // CHECK9-NEXT: entry:
2304 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2305 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2306 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2307 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2308 // CHECK9-NEXT: ret void
2309 //
2310 //
2311 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2312 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2313 // CHECK9-NEXT: entry:
2314 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2315 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2316 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2317 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2318 // CHECK9-NEXT: ret void
2319 //
2320 //
2321 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2322 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2323 // CHECK9-NEXT: entry:
2324 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2325 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2326 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2327 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2328 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2329 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2330 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4
2331 // CHECK9-NEXT: ret void
2332 //
2333 //
2334 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2335 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2336 // CHECK9-NEXT: entry:
2337 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2338 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2339 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2340 // CHECK9-NEXT: ret void
2341 //
2342 //
2343 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2344 // CHECK9-SAME: () #[[ATTR0]] {
2345 // CHECK9-NEXT: entry:
2346 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2347 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2348 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2349 // CHECK9-NEXT: ret void
2350 //
2351 //
2352 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2353 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2354 // CHECK9-NEXT: entry:
2355 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2356 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2357 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2358 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
2359 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2360 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2361 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2362 // CHECK9-NEXT: ret void
2363 //
2364 //
2365 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2366 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2367 // CHECK9-NEXT: entry:
2368 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
2369 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2370 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2371 // CHECK9: arraydestroy.body:
2372 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2373 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2374 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2375 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2376 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2377 // CHECK9: arraydestroy.done1:
2378 // CHECK9-NEXT: ret void
2379 //
2380 //
2381 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2382 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2383 // CHECK9-NEXT: entry:
2384 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2385 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2386 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2387 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
2388 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2389 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2390 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2391 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2392 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2393 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2394 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4
2395 // CHECK9-NEXT: ret void
2396 //
2397 //
2398 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2399 // CHECK9-SAME: () #[[ATTR0]] {
2400 // CHECK9-NEXT: entry:
2401 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2402 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2403 // CHECK9-NEXT: ret void
2404 //
2405 //
2406 // CHECK9-LABEL: define {{[^@]+}}@main
2407 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2408 // CHECK9-NEXT: entry:
2409 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2410 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2411 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
2412 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2413 // CHECK9-NEXT: ret i32 0
2414 //
2415 //
2416 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2417 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {
2418 // CHECK9-NEXT: entry:
2419 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2420 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2421 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2422 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8
2423 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
2424 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
2425 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2426 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
2427 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
2428 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
2429 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
2430 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
2431 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
2432 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
2433 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
2434 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4
2435 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4
2436 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8
2437 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
2438 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
2439 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
2440 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
2441 // CHECK9-NEXT: ret void
2442 //
2443 //
2444 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined
2445 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
2446 // CHECK9-NEXT: entry:
2447 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2448 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2449 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2450 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2451 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2452 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8
2453 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2454 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2455 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2456 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2457 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2458 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2459 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2460 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
2461 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
2462 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2463 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2464 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2465 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
2466 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
2467 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
2468 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
2469 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2470 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2471 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2472 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2473 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2474 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2475 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2476 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2477 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2478 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2479 // CHECK9: cond.true:
2480 // CHECK9-NEXT: br label [[COND_END:%.*]]
2481 // CHECK9: cond.false:
2482 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2483 // CHECK9-NEXT: br label [[COND_END]]
2484 // CHECK9: cond.end:
2485 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2486 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2487 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2488 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2489 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2490 // CHECK9: omp.inner.for.cond:
2491 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2492 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2493 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2494 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2495 // CHECK9: omp.inner.for.body:
2496 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2497 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2498 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2499 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2500 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4
2501 // CHECK9-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4
2502 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8
2503 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8
2504 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4
2505 // CHECK9-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4
2506 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8
2507 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
2508 // CHECK9-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
2509 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
2510 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
2511 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2512 // CHECK9: omp.inner.for.inc:
2513 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2514 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2515 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2516 // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2517 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
2518 // CHECK9: omp.inner.for.end:
2519 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2520 // CHECK9: omp.loop.exit:
2521 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2522 // CHECK9-NEXT: ret void
2523 //
2524 //
2525 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined
2526 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {
2527 // CHECK9-NEXT: entry:
2528 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2529 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2530 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2531 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2532 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
2533 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
2534 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2535 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8
2536 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2537 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2538 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2539 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2540 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2541 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2542 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
2543 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2544 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2545 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2546 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2547 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2548 // CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
2549 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
2550 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
2551 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
2552 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2553 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
2554 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2555 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2556 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2557 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
2558 // CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2559 // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
2560 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2561 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2562 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2563 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2564 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2565 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2566 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2567 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2568 // CHECK9: cond.true:
2569 // CHECK9-NEXT: br label [[COND_END:%.*]]
2570 // CHECK9: cond.false:
2571 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2572 // CHECK9-NEXT: br label [[COND_END]]
2573 // CHECK9: cond.end:
2574 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2575 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2576 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2577 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2578 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2579 // CHECK9: omp.inner.for.cond:
2580 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2581 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2582 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2583 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2584 // CHECK9: omp.inner.for.body:
2585 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2586 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2587 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2588 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2589 // CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4
2590 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8
2591 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP10]], align 4
2592 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
2593 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
2594 // CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8
2595 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
2596 // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8
2597 // CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
2598 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
2599 // CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8
2600 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
2601 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2602 // CHECK9: omp.body.continue:
2603 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2604 // CHECK9: omp.inner.for.inc:
2605 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2606 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
2607 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2608 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
2609 // CHECK9: omp.inner.for.end:
2610 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2611 // CHECK9: omp.loop.exit:
2612 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
2613 // CHECK9-NEXT: ret void
2614 //
2615 //
2616 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp
2617 // CHECK9-SAME: () #[[ATTR0]] {
2618 // CHECK9-NEXT: entry:
2619 // CHECK9-NEXT: call void @__cxx_global_var_init()
2620 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
2621 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
2622 // CHECK9-NEXT: ret void
2623 //
LLVM monorepo