clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // expected-no-diagnostics
   3 #ifndef HEADER
   4 #define HEADER
   5
   6 // Test host codegen.
   7 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
  10 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
  11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
  13
  14 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
  15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
  17 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
  18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
  20 #ifdef CK1
  21
  22 template <typename T, int X, long long Y>
  23 struct SS{
  24   T a[X][Y];
  25
  26   int foo(void) {
  27
  28     #pragma omp target
  29     #pragma omp teams distribute simd collapse(2)
  30     for(int i = 0; i < X; i++) {
  31       for(int j = 0; j < Y; j++) {
  32         a[i][j] = (T)0;
  33       }
  34     }
  35
  36     // discard loop variables not needed here
  37
  38     return a[0][0];
  39   }
  40 };
  41
  42 int teams_template_struct(void) {
  43   SS<int, 123, 456> V;
  44   return V.foo();
  45
  46 }
  47
  48 #endif // CK1
  49
  50 // Test host codegen.
  51 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
  52 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  53 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  54 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
  55 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  56 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  57
  58 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
  59 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  60 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13
  61 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
  62 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  63 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15
  64 #ifdef CK2
  65
  66 template <typename T, int n, int m>
  67 int tmain(T argc) {
  68   T a[n][m];
  69   #pragma omp target
  70   #pragma omp teams distribute simd collapse(2)
  71   for(int i = 0; i < n; i++) {
  72     for(int j = 0; j < m; j++) {
  73       a[i][j] = (T)0;
  74     }
  75   }
  76   return 0;
  77 }
  78
  79 int main (int argc, char **argv) {
  80   int n = 100;
  81   int m = 2;
  82   int a[n][m];
  83   #pragma omp target
  84   #pragma omp teams distribute simd collapse(2)
  85   for(int i = 0; i < n; i++) {
  86     for(int j = 0; j < m; j++) {
  87       a[i][j] = 0;
  88     }
  89   }
  90   return tmain<int, 10, 2>(argc);
  91 }
  92
  93
  94
  95
  96
  97 // discard loop variables not needed here
  98
  99 #endif // CK2
 100 #endif // #ifndef HEADER
 101 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv
 102 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 103 // CHECK1-NEXT:  entry:
 104 // CHECK1-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 105 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
 106 // CHECK1-NEXT:    ret i32 [[CALL]]
 107 //
 108 //
 109 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
 110 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
 111 // CHECK1-NEXT:  entry:
 112 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 113 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
 114 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
 115 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
 116 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 117 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 118 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 119 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 120 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 121 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 122 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 123 // CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 8
 124 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 125 // CHECK1-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8
 126 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 127 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 128 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 129 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 130 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 131 // CHECK1-NEXT:    store i32 3, ptr [[TMP5]], align 4
 132 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 133 // CHECK1-NEXT:    store i32 1, ptr [[TMP6]], align 4
 134 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 135 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8
 136 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 137 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8
 138 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 139 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 8
 140 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 141 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 8
 142 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 143 // CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8
 144 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 145 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 146 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 147 // CHECK1-NEXT:    store i64 56088, ptr [[TMP13]], align 8
 148 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 149 // CHECK1-NEXT:    store i64 0, ptr [[TMP14]], align 8
 150 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 151 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
 152 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 153 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
 154 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 155 // CHECK1-NEXT:    store i32 0, ptr [[TMP17]], align 4
 156 // CHECK1-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])
 157 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 158 // CHECK1-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 159 // CHECK1:       omp_offload.failed:
 160 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]
 161 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 162 // CHECK1:       omp_offload.cont:
 163 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 164 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0
 165 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0
 166 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
 167 // CHECK1-NEXT:    ret i32 [[TMP20]]
 168 //
 169 //
 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
 171 // CHECK1-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
 172 // CHECK1-NEXT:  entry:
 173 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 174 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 175 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 176 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])
 177 // CHECK1-NEXT:    ret void
 178 //
 179 //
 180 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined
 181 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {
 182 // CHECK1-NEXT:  entry:
 183 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 184 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 185 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 186 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 187 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 188 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 189 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 190 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 191 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 192 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 193 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 194 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 195 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 196 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 197 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 198 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 199 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 200 // CHECK1-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4
 201 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 202 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 203 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 204 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 205 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 206 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 207 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
 208 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 209 // CHECK1:       cond.true:
 210 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 211 // CHECK1:       cond.false:
 212 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 213 // CHECK1-NEXT:    br label [[COND_END]]
 214 // CHECK1:       cond.end:
 215 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 216 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 217 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 218 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 219 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 220 // CHECK1:       omp.inner.for.cond:
 221 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
 222 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
 223 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 224 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 225 // CHECK1:       omp.inner.for.body:
 226 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 227 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
 228 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 229 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 230 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
 231 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 232 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 233 // CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
 234 // CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
 235 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
 236 // CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 237 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
 238 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]
 239 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0
 240 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
 241 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 242 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
 243 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]
 244 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
 245 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
 246 // CHECK1-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]]
 247 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 248 // CHECK1:       omp.body.continue:
 249 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 250 // CHECK1:       omp.inner.for.inc:
 251 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 252 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
 253 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 254 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
 255 // CHECK1:       omp.inner.for.end:
 256 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 257 // CHECK1:       omp.loop.exit:
 258 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 259 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 260 // CHECK1-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
 261 // CHECK1-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 262 // CHECK1:       .omp.final.then:
 263 // CHECK1-NEXT:    store i32 123, ptr [[I]], align 4
 264 // CHECK1-NEXT:    store i32 456, ptr [[J]], align 4
 265 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 266 // CHECK1:       .omp.final.done:
 267 // CHECK1-NEXT:    ret void
 268 //
 269 //
 270 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv
 271 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 272 // CHECK3-NEXT:  entry:
 273 // CHECK3-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 274 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
 275 // CHECK3-NEXT:    ret i32 [[CALL]]
 276 //
 277 //
 278 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
 279 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
 280 // CHECK3-NEXT:  entry:
 281 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 282 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
 283 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
 284 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
 285 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 286 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 287 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 288 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 289 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 290 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 291 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 292 // CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 4
 293 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 294 // CHECK3-NEXT:    store ptr [[A]], ptr [[TMP1]], align 4
 295 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
 296 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
 297 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 298 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 299 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 300 // CHECK3-NEXT:    store i32 3, ptr [[TMP5]], align 4
 301 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 302 // CHECK3-NEXT:    store i32 1, ptr [[TMP6]], align 4
 303 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 304 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 4
 305 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 306 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 4
 307 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 308 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 4
 309 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 310 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 4
 311 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 312 // CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4
 313 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 314 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
 315 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 316 // CHECK3-NEXT:    store i64 56088, ptr [[TMP13]], align 8
 317 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 318 // CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 8
 319 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 320 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
 321 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 322 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
 323 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 324 // CHECK3-NEXT:    store i32 0, ptr [[TMP17]], align 4
 325 // CHECK3-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])
 326 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 327 // CHECK3-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 328 // CHECK3:       omp_offload.failed:
 329 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]
 330 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 331 // CHECK3:       omp_offload.cont:
 332 // CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 333 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0
 334 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0
 335 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
 336 // CHECK3-NEXT:    ret i32 [[TMP20]]
 337 //
 338 //
 339 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
 340 // CHECK3-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
 341 // CHECK3-NEXT:  entry:
 342 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 343 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 344 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 345 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])
 346 // CHECK3-NEXT:    ret void
 347 //
 348 //
 349 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined
 350 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {
 351 // CHECK3-NEXT:  entry:
 352 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 353 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 354 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 355 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 356 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 357 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 358 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 359 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 360 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 361 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 362 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 363 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
 364 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 365 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 366 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 367 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 368 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 369 // CHECK3-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4
 370 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 371 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 372 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 373 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 374 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 375 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 376 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
 377 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 378 // CHECK3:       cond.true:
 379 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 380 // CHECK3:       cond.false:
 381 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 382 // CHECK3-NEXT:    br label [[COND_END]]
 383 // CHECK3:       cond.end:
 384 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 385 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 386 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 387 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 388 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 389 // CHECK3:       omp.inner.for.cond:
 390 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 391 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 392 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 393 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 394 // CHECK3:       omp.inner.for.body:
 395 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 396 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
 397 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 398 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 399 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 400 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 401 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 402 // CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
 403 // CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
 404 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
 405 // CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 406 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
 407 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]
 408 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0
 409 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 410 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]]
 411 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]
 412 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]
 413 // CHECK3-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]]
 414 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 415 // CHECK3:       omp.body.continue:
 416 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 417 // CHECK3:       omp.inner.for.inc:
 418 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 419 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
 420 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 421 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 422 // CHECK3:       omp.inner.for.end:
 423 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 424 // CHECK3:       omp.loop.exit:
 425 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 426 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 427 // CHECK3-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
 428 // CHECK3-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 429 // CHECK3:       .omp.final.then:
 430 // CHECK3-NEXT:    store i32 123, ptr [[I]], align 4
 431 // CHECK3-NEXT:    store i32 456, ptr [[J]], align 4
 432 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 433 // CHECK3:       .omp.final.done:
 434 // CHECK3-NEXT:    ret void
 435 //
 436 //
 437 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv
 438 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 439 // CHECK5-NEXT:  entry:
 440 // CHECK5-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 441 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
 442 // CHECK5-NEXT:    ret i32 [[CALL]]
 443 //
 444 //
 445 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
 446 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
 447 // CHECK5-NEXT:  entry:
 448 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 449 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 450 // CHECK5-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 451 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 452 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 453 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 454 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
 455 // CHECK5-NEXT:    [[J:%.*]] = alloca i32, align 4
 456 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 457 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 458 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 459 // CHECK5-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4
 460 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 461 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 462 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 463 // CHECK5:       omp.inner.for.cond:
 464 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
 465 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
 466 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 467 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 468 // CHECK5:       omp.inner.for.body:
 469 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 470 // CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
 471 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 472 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 473 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
 474 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 475 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 476 // CHECK5-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
 477 // CHECK5-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
 478 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
 479 // CHECK5-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 480 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
 481 // CHECK5-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]
 482 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 483 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
 484 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
 485 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
 486 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]
 487 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
 488 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
 489 // CHECK5-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]
 490 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 491 // CHECK5:       omp.body.continue:
 492 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 493 // CHECK5:       omp.inner.for.inc:
 494 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 495 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
 496 // CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 497 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
 498 // CHECK5:       omp.inner.for.end:
 499 // CHECK5-NEXT:    store i32 123, ptr [[I]], align 4
 500 // CHECK5-NEXT:    store i32 456, ptr [[J]], align 4
 501 // CHECK5-NEXT:    [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 502 // CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0
 503 // CHECK5-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0
 504 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4
 505 // CHECK5-NEXT:    ret i32 [[TMP9]]
 506 //
 507 //
 508 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv
 509 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
 510 // CHECK7-NEXT:  entry:
 511 // CHECK7-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 512 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
 513 // CHECK7-NEXT:    ret i32 [[CALL]]
 514 //
 515 //
 516 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
 517 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
 518 // CHECK7-NEXT:  entry:
 519 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 520 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 521 // CHECK7-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 522 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 523 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 524 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 525 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
 526 // CHECK7-NEXT:    [[J:%.*]] = alloca i32, align 4
 527 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 528 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 529 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 530 // CHECK7-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4
 531 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 532 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 533 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 534 // CHECK7:       omp.inner.for.cond:
 535 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
 536 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
 537 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 538 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 539 // CHECK7:       omp.inner.for.body:
 540 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 541 // CHECK7-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
 542 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 543 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 544 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
 545 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 546 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 547 // CHECK7-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
 548 // CHECK7-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
 549 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
 550 // CHECK7-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 551 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
 552 // CHECK7-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]
 553 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 554 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
 555 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]
 556 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]
 557 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]
 558 // CHECK7-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]
 559 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 560 // CHECK7:       omp.body.continue:
 561 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 562 // CHECK7:       omp.inner.for.inc:
 563 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 564 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
 565 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 566 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
 567 // CHECK7:       omp.inner.for.end:
 568 // CHECK7-NEXT:    store i32 123, ptr [[I]], align 4
 569 // CHECK7-NEXT:    store i32 456, ptr [[J]], align 4
 570 // CHECK7-NEXT:    [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 571 // CHECK7-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0
 572 // CHECK7-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0
 573 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
 574 // CHECK7-NEXT:    ret i32 [[TMP9]]
 575 //
 576 //
 577 // CHECK9-LABEL: define {{[^@]+}}@main
 578 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
 579 // CHECK9-NEXT:  entry:
 580 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 581 // CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
 582 // CHECK9-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
 583 // CHECK9-NEXT:    [[N:%.*]] = alloca i32, align 4
 584 // CHECK9-NEXT:    [[M:%.*]] = alloca i32, align 4
 585 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 586 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 587 // CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
 588 // CHECK9-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 589 // CHECK9-NEXT:    [[M_CASTED:%.*]] = alloca i64, align 8
 590 // CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 591 // CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 592 // CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 593 // CHECK9-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
 594 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 595 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 596 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 597 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 598 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
 599 // CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 600 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 601 // CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
 602 // CHECK9-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
 603 // CHECK9-NEXT:    store i32 100, ptr [[N]], align 4
 604 // CHECK9-NEXT:    store i32 2, ptr [[M]], align 4
 605 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4
 606 // CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
 607 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 4
 608 // CHECK9-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
 609 // CHECK9-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
 610 // CHECK9-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
 611 // CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
 612 // CHECK9-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
 613 // CHECK9-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
 614 // CHECK9-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
 615 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 4
 616 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[N_CASTED]], align 4
 617 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
 618 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[M]], align 4
 619 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[M_CASTED]], align 4
 620 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[M_CASTED]], align 8
 621 // CHECK9-NEXT:    [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
 622 // CHECK9-NEXT:    [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
 623 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false)
 624 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 625 // CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP12]], align 8
 626 // CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 627 // CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP13]], align 8
 628 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 629 // CHECK9-NEXT:    store ptr null, ptr [[TMP14]], align 8
 630 // CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 631 // CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP15]], align 8
 632 // CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 633 // CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP16]], align 8
 634 // CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 635 // CHECK9-NEXT:    store ptr null, ptr [[TMP17]], align 8
 636 // CHECK9-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 637 // CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP18]], align 8
 638 // CHECK9-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 639 // CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP19]], align 8
 640 // CHECK9-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 641 // CHECK9-NEXT:    store ptr null, ptr [[TMP20]], align 8
 642 // CHECK9-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 643 // CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP21]], align 8
 644 // CHECK9-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 645 // CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP22]], align 8
 646 // CHECK9-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 647 // CHECK9-NEXT:    store ptr null, ptr [[TMP23]], align 8
 648 // CHECK9-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 649 // CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 8
 650 // CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 651 // CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP25]], align 8
 652 // CHECK9-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
 653 // CHECK9-NEXT:    store i64 [[TMP11]], ptr [[TMP26]], align 8
 654 // CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 655 // CHECK9-NEXT:    store ptr null, ptr [[TMP27]], align 8
 656 // CHECK9-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 657 // CHECK9-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 658 // CHECK9-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 659 // CHECK9-NEXT:    [[TMP31:%.*]] = load i32, ptr [[N]], align 4
 660 // CHECK9-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_]], align 4
 661 // CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[M]], align 4
 662 // CHECK9-NEXT:    store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 663 // CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 664 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP33]], 0
 665 // CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 666 // CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
 667 // CHECK9-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 668 // CHECK9-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP34]], 0
 669 // CHECK9-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
 670 // CHECK9-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
 671 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
 672 // CHECK9-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
 673 // CHECK9-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
 674 // CHECK9-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 675 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP35]], 1
 676 // CHECK9-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 677 // CHECK9-NEXT:    store i32 3, ptr [[TMP36]], align 4
 678 // CHECK9-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 679 // CHECK9-NEXT:    store i32 5, ptr [[TMP37]], align 4
 680 // CHECK9-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 681 // CHECK9-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 8
 682 // CHECK9-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 683 // CHECK9-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 8
 684 // CHECK9-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 685 // CHECK9-NEXT:    store ptr [[TMP30]], ptr [[TMP40]], align 8
 686 // CHECK9-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 687 // CHECK9-NEXT:    store ptr @.offload_maptypes, ptr [[TMP41]], align 8
 688 // CHECK9-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 689 // CHECK9-NEXT:    store ptr null, ptr [[TMP42]], align 8
 690 // CHECK9-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 691 // CHECK9-NEXT:    store ptr null, ptr [[TMP43]], align 8
 692 // CHECK9-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 693 // CHECK9-NEXT:    store i64 [[ADD]], ptr [[TMP44]], align 8
 694 // CHECK9-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 695 // CHECK9-NEXT:    store i64 0, ptr [[TMP45]], align 8
 696 // CHECK9-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 697 // CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4
 698 // CHECK9-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 699 // CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP47]], align 4
 700 // CHECK9-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 701 // CHECK9-NEXT:    store i32 0, ptr [[TMP48]], align 4
 702 // CHECK9-NEXT:    [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]])
 703 // CHECK9-NEXT:    [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
 704 // CHECK9-NEXT:    br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 705 // CHECK9:       omp_offload.failed:
 706 // CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
 707 // CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 708 // CHECK9:       omp_offload.cont:
 709 // CHECK9-NEXT:    [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
 710 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
 711 // CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 712 // CHECK9-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
 713 // CHECK9-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP52]])
 714 // CHECK9-NEXT:    [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
 715 // CHECK9-NEXT:    ret i32 [[TMP53]]
 716 //
 717 //
 718 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
 719 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
 720 // CHECK9-NEXT:  entry:
 721 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 722 // CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca i64, align 8
 723 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
 724 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
 725 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 726 // CHECK9-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 727 // CHECK9-NEXT:    store i64 [[M]], ptr [[M_ADDR]], align 8
 728 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
 729 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
 730 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 731 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
 732 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
 733 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 734 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]])
 735 // CHECK9-NEXT:    ret void
 736 //
 737 //
 738 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined
 739 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
 740 // CHECK9-NEXT:  entry:
 741 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 742 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 743 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 8
 744 // CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca ptr, align 8
 745 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
 746 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
 747 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 748 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 749 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 750 // CHECK9-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
 751 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 752 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
 753 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
 754 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
 755 // CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4
 756 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 757 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 758 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 759 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 760 // CHECK9-NEXT:    [[I11:%.*]] = alloca i32, align 4
 761 // CHECK9-NEXT:    [[J12:%.*]] = alloca i32, align 4
 762 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 763 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 764 // CHECK9-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 8
 765 // CHECK9-NEXT:    store ptr [[M]], ptr [[M_ADDR]], align 8
 766 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
 767 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
 768 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 769 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8
 770 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 8
 771 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
 772 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
 773 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 774 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
 775 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
 776 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4
 777 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4
 778 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 779 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
 780 // CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 781 // CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
 782 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 783 // CHECK9-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
 784 // CHECK9-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
 785 // CHECK9-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
 786 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
 787 // CHECK9-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
 788 // CHECK9-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
 789 // CHECK9-NEXT:    store i32 0, ptr [[I]], align 4
 790 // CHECK9-NEXT:    store i32 0, ptr [[J]], align 4
 791 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 792 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
 793 // CHECK9-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
 794 // CHECK9:       land.lhs.true:
 795 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 796 // CHECK9-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
 797 // CHECK9-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
 798 // CHECK9:       omp.precond.then:
 799 // CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 800 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
 801 // CHECK9-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8
 802 // CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 803 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 804 // CHECK9-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 805 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
 806 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
 807 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 808 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
 809 // CHECK9-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
 810 // CHECK9-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 811 // CHECK9:       cond.true:
 812 // CHECK9-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
 813 // CHECK9-NEXT:    br label [[COND_END:%.*]]
 814 // CHECK9:       cond.false:
 815 // CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 816 // CHECK9-NEXT:    br label [[COND_END]]
 817 // CHECK9:       cond.end:
 818 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
 819 // CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
 820 // CHECK9-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 821 // CHECK9-NEXT:    store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8
 822 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 823 // CHECK9:       omp.inner.for.cond:
 824 // CHECK9-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 825 // CHECK9-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
 826 // CHECK9-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
 827 // CHECK9-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 828 // CHECK9:       omp.inner.for.body:
 829 // CHECK9-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 830 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
 831 // CHECK9-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
 832 // CHECK9-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
 833 // CHECK9-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
 834 // CHECK9-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
 835 // CHECK9-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
 836 // CHECK9-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
 837 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
 838 // CHECK9-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
 839 // CHECK9-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]
 840 // CHECK9-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 841 // CHECK9-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 842 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
 843 // CHECK9-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
 844 // CHECK9-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
 845 // CHECK9-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
 846 // CHECK9-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
 847 // CHECK9-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
 848 // CHECK9-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
 849 // CHECK9-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
 850 // CHECK9-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
 851 // CHECK9-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
 852 // CHECK9-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
 853 // CHECK9-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
 854 // CHECK9-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
 855 // CHECK9-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
 856 // CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
 857 // CHECK9-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
 858 // CHECK9-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]
 859 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]
 860 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
 861 // CHECK9-NEXT:    [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
 862 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP28]]
 863 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]
 864 // CHECK9-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64
 865 // CHECK9-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]]
 866 // CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP5]]
 867 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 868 // CHECK9:       omp.body.continue:
 869 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 870 // CHECK9:       omp.inner.for.inc:
 871 // CHECK9-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 872 // CHECK9-NEXT:    [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1
 873 // CHECK9-NEXT:    store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 874 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 875 // CHECK9:       omp.inner.for.end:
 876 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 877 // CHECK9:       omp.loop.exit:
 878 // CHECK9-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 879 // CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
 880 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]])
 881 // CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 882 // CHECK9-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
 883 // CHECK9-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 884 // CHECK9:       .omp.final.then:
 885 // CHECK9-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 886 // CHECK9-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP35]], 0
 887 // CHECK9-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
 888 // CHECK9-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
 889 // CHECK9-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
 890 // CHECK9-NEXT:    store i32 [[ADD42]], ptr [[I11]], align 4
 891 // CHECK9-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 892 // CHECK9-NEXT:    [[SUB43:%.*]] = sub nsw i32 [[TMP36]], 0
 893 // CHECK9-NEXT:    [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1
 894 // CHECK9-NEXT:    [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1
 895 // CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 0, [[MUL45]]
 896 // CHECK9-NEXT:    store i32 [[ADD46]], ptr [[J12]], align 4
 897 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 898 // CHECK9:       .omp.final.done:
 899 // CHECK9-NEXT:    br label [[OMP_PRECOND_END]]
 900 // CHECK9:       omp.precond.end:
 901 // CHECK9-NEXT:    ret void
 902 //
 903 //
 904 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
 905 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {
 906 // CHECK9-NEXT:  entry:
 907 // CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
 908 // CHECK9-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4
 909 // CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
 910 // CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
 911 // CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
 912 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 913 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 914 // CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 915 // CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
 916 // CHECK9-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 917 // CHECK9-NEXT:    store ptr [[A]], ptr [[TMP0]], align 8
 918 // CHECK9-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 919 // CHECK9-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8
 920 // CHECK9-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 921 // CHECK9-NEXT:    store ptr null, ptr [[TMP2]], align 8
 922 // CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 923 // CHECK9-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 924 // CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 925 // CHECK9-NEXT:    store i32 3, ptr [[TMP5]], align 4
 926 // CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 927 // CHECK9-NEXT:    store i32 1, ptr [[TMP6]], align 4
 928 // CHECK9-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 929 // CHECK9-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8
 930 // CHECK9-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 931 // CHECK9-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8
 932 // CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 933 // CHECK9-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 8
 934 // CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 935 // CHECK9-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8
 936 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 937 // CHECK9-NEXT:    store ptr null, ptr [[TMP11]], align 8
 938 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 939 // CHECK9-NEXT:    store ptr null, ptr [[TMP12]], align 8
 940 // CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 941 // CHECK9-NEXT:    store i64 20, ptr [[TMP13]], align 8
 942 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 943 // CHECK9-NEXT:    store i64 0, ptr [[TMP14]], align 8
 944 // CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 945 // CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
 946 // CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 947 // CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
 948 // CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 949 // CHECK9-NEXT:    store i32 0, ptr [[TMP17]], align 4
 950 // CHECK9-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]])
 951 // CHECK9-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 952 // CHECK9-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 953 // CHECK9:       omp_offload.failed:
 954 // CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69(ptr [[A]]) #[[ATTR3]]
 955 // CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 956 // CHECK9:       omp_offload.cont:
 957 // CHECK9-NEXT:    ret i32 0
 958 //
 959 //
 960 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69
 961 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
 962 // CHECK9-NEXT:  entry:
 963 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 964 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 965 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 966 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]])
 967 // CHECK9-NEXT:    ret void
 968 //
 969 //
 970 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined
 971 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
 972 // CHECK9-NEXT:  entry:
 973 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 974 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 975 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 976 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 977 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 978 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 979 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 980 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 981 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 982 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 983 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
 984 // CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4
 985 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 986 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 987 // CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 988 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 989 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 990 // CHECK9-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4
 991 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 992 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 993 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 994 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 995 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 996 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 997 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
 998 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 999 // CHECK9:       cond.true:
1000 // CHECK9-NEXT:    br label [[COND_END:%.*]]
1001 // CHECK9:       cond.false:
1002 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1003 // CHECK9-NEXT:    br label [[COND_END]]
1004 // CHECK9:       cond.end:
1005 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1006 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1007 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1008 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1009 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1010 // CHECK9:       omp.inner.for.cond:
1011 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
1012 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
1013 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1014 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1015 // CHECK9:       omp.inner.for.body:
1016 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1017 // CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1018 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1019 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1020 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1021 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1022 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1023 // CHECK9-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1024 // CHECK9-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1025 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1026 // CHECK9-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1027 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1028 // CHECK9-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]
1029 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1030 // CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1031 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1032 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]
1033 // CHECK9-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
1034 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1035 // CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]]
1036 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1037 // CHECK9:       omp.body.continue:
1038 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1039 // CHECK9:       omp.inner.for.inc:
1040 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1041 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
1042 // CHECK9-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1043 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
1044 // CHECK9:       omp.inner.for.end:
1045 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1046 // CHECK9:       omp.loop.exit:
1047 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
1048 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1049 // CHECK9-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1050 // CHECK9-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1051 // CHECK9:       .omp.final.then:
1052 // CHECK9-NEXT:    store i32 10, ptr [[I]], align 4
1053 // CHECK9-NEXT:    store i32 2, ptr [[J]], align 4
1054 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1055 // CHECK9:       .omp.final.done:
1056 // CHECK9-NEXT:    ret void
1057 //
1058 //
1059 // CHECK11-LABEL: define {{[^@]+}}@main
1060 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1061 // CHECK11-NEXT:  entry:
1062 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1063 // CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1064 // CHECK11-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 4
1065 // CHECK11-NEXT:    [[N:%.*]] = alloca i32, align 4
1066 // CHECK11-NEXT:    [[M:%.*]] = alloca i32, align 4
1067 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
1068 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1069 // CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1070 // CHECK11-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
1071 // CHECK11-NEXT:    [[M_CASTED:%.*]] = alloca i32, align 4
1072 // CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1073 // CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1074 // CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1075 // CHECK11-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
1076 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1077 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1078 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1079 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1080 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1081 // CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1082 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1083 // CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1084 // CHECK11-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
1085 // CHECK11-NEXT:    store i32 100, ptr [[N]], align 4
1086 // CHECK11-NEXT:    store i32 2, ptr [[M]], align 4
1087 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1088 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 4
1089 // CHECK11-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1090 // CHECK11-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1091 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1092 // CHECK11-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1093 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
1094 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
1095 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 4
1096 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[N_CASTED]], align 4
1097 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
1098 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[M]], align 4
1099 // CHECK11-NEXT:    store i32 [[TMP6]], ptr [[M_CASTED]], align 4
1100 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M_CASTED]], align 4
1101 // CHECK11-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1102 // CHECK11-NEXT:    [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
1103 // CHECK11-NEXT:    [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
1104 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false)
1105 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1106 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP11]], align 4
1107 // CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1108 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP12]], align 4
1109 // CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1110 // CHECK11-NEXT:    store ptr null, ptr [[TMP13]], align 4
1111 // CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1112 // CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP14]], align 4
1113 // CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1114 // CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP15]], align 4
1115 // CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1116 // CHECK11-NEXT:    store ptr null, ptr [[TMP16]], align 4
1117 // CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1118 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP17]], align 4
1119 // CHECK11-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1120 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP18]], align 4
1121 // CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1122 // CHECK11-NEXT:    store ptr null, ptr [[TMP19]], align 4
1123 // CHECK11-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1124 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
1125 // CHECK11-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1126 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP21]], align 4
1127 // CHECK11-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1128 // CHECK11-NEXT:    store ptr null, ptr [[TMP22]], align 4
1129 // CHECK11-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1130 // CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
1131 // CHECK11-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1132 // CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 4
1133 // CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1134 // CHECK11-NEXT:    store i64 [[TMP10]], ptr [[TMP25]], align 4
1135 // CHECK11-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1136 // CHECK11-NEXT:    store ptr null, ptr [[TMP26]], align 4
1137 // CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1138 // CHECK11-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1139 // CHECK11-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1140 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[N]], align 4
1141 // CHECK11-NEXT:    store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 4
1142 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[M]], align 4
1143 // CHECK11-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1144 // CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1145 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP32]], 0
1146 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1147 // CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1148 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1149 // CHECK11-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP33]], 0
1150 // CHECK11-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1151 // CHECK11-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1152 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1153 // CHECK11-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1154 // CHECK11-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1155 // CHECK11-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1156 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP34]], 1
1157 // CHECK11-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1158 // CHECK11-NEXT:    store i32 3, ptr [[TMP35]], align 4
1159 // CHECK11-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1160 // CHECK11-NEXT:    store i32 5, ptr [[TMP36]], align 4
1161 // CHECK11-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1162 // CHECK11-NEXT:    store ptr [[TMP27]], ptr [[TMP37]], align 4
1163 // CHECK11-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1164 // CHECK11-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 4
1165 // CHECK11-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1166 // CHECK11-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 4
1167 // CHECK11-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1168 // CHECK11-NEXT:    store ptr @.offload_maptypes, ptr [[TMP40]], align 4
1169 // CHECK11-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1170 // CHECK11-NEXT:    store ptr null, ptr [[TMP41]], align 4
1171 // CHECK11-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1172 // CHECK11-NEXT:    store ptr null, ptr [[TMP42]], align 4
1173 // CHECK11-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1174 // CHECK11-NEXT:    store i64 [[ADD]], ptr [[TMP43]], align 8
1175 // CHECK11-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1176 // CHECK11-NEXT:    store i64 0, ptr [[TMP44]], align 8
1177 // CHECK11-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1178 // CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
1179 // CHECK11-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1180 // CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 4
1181 // CHECK11-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1182 // CHECK11-NEXT:    store i32 0, ptr [[TMP47]], align 4
1183 // CHECK11-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]])
1184 // CHECK11-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
1185 // CHECK11-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1186 // CHECK11:       omp_offload.failed:
1187 // CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
1188 // CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1189 // CHECK11:       omp_offload.cont:
1190 // CHECK11-NEXT:    [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1191 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
1192 // CHECK11-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1193 // CHECK11-NEXT:    [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
1194 // CHECK11-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP51]])
1195 // CHECK11-NEXT:    [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
1196 // CHECK11-NEXT:    ret i32 [[TMP52]]
1197 //
1198 //
1199 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
1200 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
1201 // CHECK11-NEXT:  entry:
1202 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1203 // CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca i32, align 4
1204 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
1205 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
1206 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1207 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1208 // CHECK11-NEXT:    store i32 [[M]], ptr [[M_ADDR]], align 4
1209 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1210 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1211 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1212 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1213 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1214 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1215 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]])
1216 // CHECK11-NEXT:    ret void
1217 //
1218 //
1219 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined
1220 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1221 // CHECK11-NEXT:  entry:
1222 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1223 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1224 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 4
1225 // CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca ptr, align 4
1226 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
1227 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
1228 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1229 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1230 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1231 // CHECK11-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
1232 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1233 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1234 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
1235 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
1236 // CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 4
1237 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1238 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1239 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1240 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1241 // CHECK11-NEXT:    [[I11:%.*]] = alloca i32, align 4
1242 // CHECK11-NEXT:    [[J12:%.*]] = alloca i32, align 4
1243 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1244 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1245 // CHECK11-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 4
1246 // CHECK11-NEXT:    store ptr [[M]], ptr [[M_ADDR]], align 4
1247 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1248 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1249 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1250 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4
1251 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 4
1252 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1253 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1254 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1255 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1256 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
1257 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4
1258 // CHECK11-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4
1259 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1260 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
1261 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1262 // CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1263 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1264 // CHECK11-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
1265 // CHECK11-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1266 // CHECK11-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1267 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
1268 // CHECK11-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1269 // CHECK11-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
1270 // CHECK11-NEXT:    store i32 0, ptr [[I]], align 4
1271 // CHECK11-NEXT:    store i32 0, ptr [[J]], align 4
1272 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1273 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
1274 // CHECK11-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1275 // CHECK11:       land.lhs.true:
1276 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1277 // CHECK11-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
1278 // CHECK11-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1279 // CHECK11:       omp.precond.then:
1280 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1281 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1282 // CHECK11-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8
1283 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1284 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1285 // CHECK11-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1286 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
1287 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
1288 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1289 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1290 // CHECK11-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
1291 // CHECK11-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1292 // CHECK11:       cond.true:
1293 // CHECK11-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1294 // CHECK11-NEXT:    br label [[COND_END:%.*]]
1295 // CHECK11:       cond.false:
1296 // CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1297 // CHECK11-NEXT:    br label [[COND_END]]
1298 // CHECK11:       cond.end:
1299 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
1300 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
1301 // CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1302 // CHECK11-NEXT:    store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8
1303 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1304 // CHECK11:       omp.inner.for.cond:
1305 // CHECK11-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1306 // CHECK11-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
1307 // CHECK11-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
1308 // CHECK11-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1309 // CHECK11:       omp.inner.for.body:
1310 // CHECK11-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1311 // CHECK11-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1312 // CHECK11-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
1313 // CHECK11-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
1314 // CHECK11-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
1315 // CHECK11-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
1316 // CHECK11-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
1317 // CHECK11-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
1318 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
1319 // CHECK11-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
1320 // CHECK11-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]
1321 // CHECK11-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1322 // CHECK11-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1323 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1324 // CHECK11-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
1325 // CHECK11-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
1326 // CHECK11-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
1327 // CHECK11-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
1328 // CHECK11-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
1329 // CHECK11-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1330 // CHECK11-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
1331 // CHECK11-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
1332 // CHECK11-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
1333 // CHECK11-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
1334 // CHECK11-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
1335 // CHECK11-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
1336 // CHECK11-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
1337 // CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
1338 // CHECK11-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
1339 // CHECK11-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]
1340 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]
1341 // CHECK11-NEXT:    [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]
1342 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[TMP28]]
1343 // CHECK11-NEXT:    [[TMP29:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]
1344 // CHECK11-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP29]]
1345 // CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP6]]
1346 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1347 // CHECK11:       omp.body.continue:
1348 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1349 // CHECK11:       omp.inner.for.inc:
1350 // CHECK11-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1351 // CHECK11-NEXT:    [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1
1352 // CHECK11-NEXT:    store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1353 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1354 // CHECK11:       omp.inner.for.end:
1355 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1356 // CHECK11:       omp.loop.exit:
1357 // CHECK11-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1358 // CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
1359 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]])
1360 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1361 // CHECK11-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1362 // CHECK11-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1363 // CHECK11:       .omp.final.then:
1364 // CHECK11-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1365 // CHECK11-NEXT:    [[SUB38:%.*]] = sub nsw i32 [[TMP35]], 0
1366 // CHECK11-NEXT:    [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1
1367 // CHECK11-NEXT:    [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1
1368 // CHECK11-NEXT:    [[ADD41:%.*]] = add nsw i32 0, [[MUL40]]
1369 // CHECK11-NEXT:    store i32 [[ADD41]], ptr [[I11]], align 4
1370 // CHECK11-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1371 // CHECK11-NEXT:    [[SUB42:%.*]] = sub nsw i32 [[TMP36]], 0
1372 // CHECK11-NEXT:    [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1
1373 // CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1
1374 // CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
1375 // CHECK11-NEXT:    store i32 [[ADD45]], ptr [[J12]], align 4
1376 // CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1377 // CHECK11:       .omp.final.done:
1378 // CHECK11-NEXT:    br label [[OMP_PRECOND_END]]
1379 // CHECK11:       omp.precond.end:
1380 // CHECK11-NEXT:    ret void
1381 //
1382 //
1383 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1384 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {
1385 // CHECK11-NEXT:  entry:
1386 // CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1387 // CHECK11-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1388 // CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
1389 // CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
1390 // CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
1391 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1392 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1393 // CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1394 // CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1395 // CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1396 // CHECK11-NEXT:    store ptr [[A]], ptr [[TMP0]], align 4
1397 // CHECK11-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1398 // CHECK11-NEXT:    store ptr [[A]], ptr [[TMP1]], align 4
1399 // CHECK11-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1400 // CHECK11-NEXT:    store ptr null, ptr [[TMP2]], align 4
1401 // CHECK11-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1402 // CHECK11-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1403 // CHECK11-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1404 // CHECK11-NEXT:    store i32 3, ptr [[TMP5]], align 4
1405 // CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1406 // CHECK11-NEXT:    store i32 1, ptr [[TMP6]], align 4
1407 // CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1408 // CHECK11-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 4
1409 // CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1410 // CHECK11-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 4
1411 // CHECK11-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1412 // CHECK11-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 4
1413 // CHECK11-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1414 // CHECK11-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4
1415 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1416 // CHECK11-NEXT:    store ptr null, ptr [[TMP11]], align 4
1417 // CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1418 // CHECK11-NEXT:    store ptr null, ptr [[TMP12]], align 4
1419 // CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1420 // CHECK11-NEXT:    store i64 20, ptr [[TMP13]], align 8
1421 // CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1422 // CHECK11-NEXT:    store i64 0, ptr [[TMP14]], align 8
1423 // CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1424 // CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
1425 // CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1426 // CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
1427 // CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1428 // CHECK11-NEXT:    store i32 0, ptr [[TMP17]], align 4
1429 // CHECK11-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]])
1430 // CHECK11-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1431 // CHECK11-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1432 // CHECK11:       omp_offload.failed:
1433 // CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69(ptr [[A]]) #[[ATTR3]]
1434 // CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1435 // CHECK11:       omp_offload.cont:
1436 // CHECK11-NEXT:    ret i32 0
1437 //
1438 //
1439 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69
1440 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1441 // CHECK11-NEXT:  entry:
1442 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1443 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1444 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1445 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]])
1446 // CHECK11-NEXT:    ret void
1447 //
1448 //
1449 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined
1450 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1451 // CHECK11-NEXT:  entry:
1452 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1453 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1454 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1455 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1456 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1457 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1458 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1459 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1460 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1461 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1462 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
1463 // CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 4
1464 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1465 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1466 // CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1467 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1468 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1469 // CHECK11-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4
1470 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1471 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1472 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1473 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1474 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1475 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1476 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1477 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1478 // CHECK11:       cond.true:
1479 // CHECK11-NEXT:    br label [[COND_END:%.*]]
1480 // CHECK11:       cond.false:
1481 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1482 // CHECK11-NEXT:    br label [[COND_END]]
1483 // CHECK11:       cond.end:
1484 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1485 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1486 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1487 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1488 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1489 // CHECK11:       omp.inner.for.cond:
1490 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
1491 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
1492 // CHECK11-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1493 // CHECK11-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1494 // CHECK11:       omp.inner.for.body:
1495 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1496 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1497 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1498 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1499 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1500 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1501 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1502 // CHECK11-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1503 // CHECK11-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1504 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1505 // CHECK11-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1506 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1507 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]
1508 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1509 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]]
1510 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]
1511 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]
1512 // CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]]
1513 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1514 // CHECK11:       omp.body.continue:
1515 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1516 // CHECK11:       omp.inner.for.inc:
1517 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1518 // CHECK11-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
1519 // CHECK11-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1520 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1521 // CHECK11:       omp.inner.for.end:
1522 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1523 // CHECK11:       omp.loop.exit:
1524 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
1525 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1526 // CHECK11-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1527 // CHECK11-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1528 // CHECK11:       .omp.final.then:
1529 // CHECK11-NEXT:    store i32 10, ptr [[I]], align 4
1530 // CHECK11-NEXT:    store i32 2, ptr [[J]], align 4
1531 // CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1532 // CHECK11:       .omp.final.done:
1533 // CHECK11-NEXT:    ret void
1534 //
1535 //
1536 // CHECK13-LABEL: define {{[^@]+}}@main
1537 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1538 // CHECK13-NEXT:  entry:
1539 // CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1540 // CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1541 // CHECK13-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
1542 // CHECK13-NEXT:    [[N:%.*]] = alloca i32, align 4
1543 // CHECK13-NEXT:    [[M:%.*]] = alloca i32, align 4
1544 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1545 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1546 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1547 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1548 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1549 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1550 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1551 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1552 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1553 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1554 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
1555 // CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 4
1556 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1557 // CHECK13-NEXT:    [[I9:%.*]] = alloca i32, align 4
1558 // CHECK13-NEXT:    [[J10:%.*]] = alloca i32, align 4
1559 // CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1560 // CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1561 // CHECK13-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
1562 // CHECK13-NEXT:    store i32 100, ptr [[N]], align 4
1563 // CHECK13-NEXT:    store i32 2, ptr [[M]], align 4
1564 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1565 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1566 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 4
1567 // CHECK13-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
1568 // CHECK13-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
1569 // CHECK13-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
1570 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1571 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
1572 // CHECK13-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
1573 // CHECK13-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
1574 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 4
1575 // CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
1576 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M]], align 4
1577 // CHECK13-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1578 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1579 // CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0
1580 // CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1581 // CHECK13-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1582 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1583 // CHECK13-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0
1584 // CHECK13-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1585 // CHECK13-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1586 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1587 // CHECK13-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1588 // CHECK13-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1589 // CHECK13-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1590 // CHECK13-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1591 // CHECK13-NEXT:    store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8
1592 // CHECK13-NEXT:    store i32 0, ptr [[I]], align 4
1593 // CHECK13-NEXT:    store i32 0, ptr [[J]], align 4
1594 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1595 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]
1596 // CHECK13-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
1597 // CHECK13:       land.lhs.true:
1598 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1599 // CHECK13-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]
1600 // CHECK13-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
1601 // CHECK13:       simd.if.then:
1602 // CHECK13-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1603 // CHECK13-NEXT:    store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 8
1604 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1605 // CHECK13:       omp.inner.for.cond:
1606 // CHECK13-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1607 // CHECK13-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
1608 // CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
1609 // CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1610 // CHECK13:       omp.inner.for.body:
1611 // CHECK13-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1612 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1613 // CHECK13-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0
1614 // CHECK13-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
1615 // CHECK13-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
1616 // CHECK13-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
1617 // CHECK13-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]
1618 // CHECK13-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
1619 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
1620 // CHECK13-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
1621 // CHECK13-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]
1622 // CHECK13-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1623 // CHECK13-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1624 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1625 // CHECK13-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0
1626 // CHECK13-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1627 // CHECK13-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1628 // CHECK13-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1629 // CHECK13-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]
1630 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1631 // CHECK13-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0
1632 // CHECK13-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1633 // CHECK13-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1634 // CHECK13-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1635 // CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1636 // CHECK13-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]
1637 // CHECK13-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1638 // CHECK13-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1639 // CHECK13-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1640 // CHECK13-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]
1641 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]
1642 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
1643 // CHECK13-NEXT:    [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
1644 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 [[TMP23]]
1645 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]
1646 // CHECK13-NEXT:    [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64
1647 // CHECK13-NEXT:    [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM33]]
1648 // CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP2]]
1649 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1650 // CHECK13:       omp.body.continue:
1651 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1652 // CHECK13:       omp.inner.for.inc:
1653 // CHECK13-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1654 // CHECK13-NEXT:    [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1
1655 // CHECK13-NEXT:    store i64 [[ADD35]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1656 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1657 // CHECK13:       omp.inner.for.end:
1658 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1659 // CHECK13-NEXT:    [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0
1660 // CHECK13-NEXT:    [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1
1661 // CHECK13-NEXT:    [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1
1662 // CHECK13-NEXT:    [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]
1663 // CHECK13-NEXT:    store i32 [[ADD39]], ptr [[I9]], align 4
1664 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1665 // CHECK13-NEXT:    [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0
1666 // CHECK13-NEXT:    [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
1667 // CHECK13-NEXT:    [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
1668 // CHECK13-NEXT:    [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
1669 // CHECK13-NEXT:    store i32 [[ADD43]], ptr [[J10]], align 4
1670 // CHECK13-NEXT:    br label [[SIMD_IF_END]]
1671 // CHECK13:       simd.if.end:
1672 // CHECK13-NEXT:    [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1673 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
1674 // CHECK13-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1675 // CHECK13-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1676 // CHECK13-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP29]])
1677 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
1678 // CHECK13-NEXT:    ret i32 [[TMP30]]
1679 //
1680 //
1681 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1682 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
1683 // CHECK13-NEXT:  entry:
1684 // CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1685 // CHECK13-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1686 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1687 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1688 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1689 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1690 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1691 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
1692 // CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 4
1693 // CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1694 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1695 // CHECK13-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4
1696 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1697 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1698 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1699 // CHECK13:       omp.inner.for.cond:
1700 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1701 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1702 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1703 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1704 // CHECK13:       omp.inner.for.body:
1705 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1706 // CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
1707 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1708 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1709 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1710 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1711 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1712 // CHECK13-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
1713 // CHECK13-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
1714 // CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
1715 // CHECK13-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
1716 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
1717 // CHECK13-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]
1718 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1719 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1720 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
1721 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]
1722 // CHECK13-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64
1723 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]
1724 // CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]]
1725 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1726 // CHECK13:       omp.body.continue:
1727 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1728 // CHECK13:       omp.inner.for.inc:
1729 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1730 // CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1731 // CHECK13-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1732 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1733 // CHECK13:       omp.inner.for.end:
1734 // CHECK13-NEXT:    store i32 10, ptr [[I]], align 4
1735 // CHECK13-NEXT:    store i32 2, ptr [[J]], align 4
1736 // CHECK13-NEXT:    ret i32 0
1737 //
1738 //
1739 // CHECK15-LABEL: define {{[^@]+}}@main
1740 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1741 // CHECK15-NEXT:  entry:
1742 // CHECK15-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1743 // CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1744 // CHECK15-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 4
1745 // CHECK15-NEXT:    [[N:%.*]] = alloca i32, align 4
1746 // CHECK15-NEXT:    [[M:%.*]] = alloca i32, align 4
1747 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
1748 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1749 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1750 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1751 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1752 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1753 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1754 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1755 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1756 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1757 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
1758 // CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 4
1759 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1760 // CHECK15-NEXT:    [[I9:%.*]] = alloca i32, align 4
1761 // CHECK15-NEXT:    [[J10:%.*]] = alloca i32, align 4
1762 // CHECK15-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1763 // CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1764 // CHECK15-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
1765 // CHECK15-NEXT:    store i32 100, ptr [[N]], align 4
1766 // CHECK15-NEXT:    store i32 2, ptr [[M]], align 4
1767 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1768 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 4
1769 // CHECK15-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1770 // CHECK15-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1771 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1772 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1773 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
1774 // CHECK15-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
1775 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 4
1776 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
1777 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[M]], align 4
1778 // CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1779 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1780 // CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0
1781 // CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1782 // CHECK15-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1783 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1784 // CHECK15-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0
1785 // CHECK15-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1786 // CHECK15-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1787 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1788 // CHECK15-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1789 // CHECK15-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1790 // CHECK15-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1791 // CHECK15-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1792 // CHECK15-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
1793 // CHECK15-NEXT:    store i32 0, ptr [[I]], align 4
1794 // CHECK15-NEXT:    store i32 0, ptr [[J]], align 4
1795 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1796 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
1797 // CHECK15-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
1798 // CHECK15:       land.lhs.true:
1799 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1800 // CHECK15-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]
1801 // CHECK15-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
1802 // CHECK15:       simd.if.then:
1803 // CHECK15-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1804 // CHECK15-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8
1805 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1806 // CHECK15:       omp.inner.for.cond:
1807 // CHECK15-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1808 // CHECK15-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]
1809 // CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]
1810 // CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1811 // CHECK15:       omp.inner.for.body:
1812 // CHECK15-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1813 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1814 // CHECK15-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0
1815 // CHECK15-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
1816 // CHECK15-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
1817 // CHECK15-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
1818 // CHECK15-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]
1819 // CHECK15-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
1820 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
1821 // CHECK15-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
1822 // CHECK15-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]
1823 // CHECK15-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1824 // CHECK15-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1825 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1826 // CHECK15-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0
1827 // CHECK15-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1828 // CHECK15-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1829 // CHECK15-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1830 // CHECK15-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]
1831 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1832 // CHECK15-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0
1833 // CHECK15-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1834 // CHECK15-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1835 // CHECK15-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1836 // CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1837 // CHECK15-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]
1838 // CHECK15-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1839 // CHECK15-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1840 // CHECK15-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1841 // CHECK15-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]
1842 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]
1843 // CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]
1844 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 [[TMP21]]
1845 // CHECK15-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]
1846 // CHECK15-NEXT:    [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP22]]
1847 // CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP3]]
1848 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1849 // CHECK15:       omp.body.continue:
1850 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1851 // CHECK15:       omp.inner.for.inc:
1852 // CHECK15-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1853 // CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1
1854 // CHECK15-NEXT:    store i64 [[ADD34]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1855 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1856 // CHECK15:       omp.inner.for.end:
1857 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1858 // CHECK15-NEXT:    [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0
1859 // CHECK15-NEXT:    [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1
1860 // CHECK15-NEXT:    [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1
1861 // CHECK15-NEXT:    [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]
1862 // CHECK15-NEXT:    store i32 [[ADD38]], ptr [[I9]], align 4
1863 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1864 // CHECK15-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0
1865 // CHECK15-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
1866 // CHECK15-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
1867 // CHECK15-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
1868 // CHECK15-NEXT:    store i32 [[ADD42]], ptr [[J10]], align 4
1869 // CHECK15-NEXT:    br label [[SIMD_IF_END]]
1870 // CHECK15:       simd.if.end:
1871 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1872 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
1873 // CHECK15-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1874 // CHECK15-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
1875 // CHECK15-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP27]])
1876 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
1877 // CHECK15-NEXT:    ret i32 [[TMP28]]
1878 //
1879 //
1880 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1881 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
1882 // CHECK15-NEXT:  entry:
1883 // CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1884 // CHECK15-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1885 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1886 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1887 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1888 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1889 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1890 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
1891 // CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 4
1892 // CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1893 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1894 // CHECK15-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4
1895 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1896 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1897 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1898 // CHECK15:       omp.inner.for.cond:
1899 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1900 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1901 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1902 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1903 // CHECK15:       omp.inner.for.body:
1904 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1905 // CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
1906 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1907 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1908 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1909 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1910 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1911 // CHECK15-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
1912 // CHECK15-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
1913 // CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
1914 // CHECK15-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
1915 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
1916 // CHECK15-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]
1917 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1918 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]
1919 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]
1920 // CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]
1921 // CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]
1922 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1923 // CHECK15:       omp.body.continue:
1924 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1925 // CHECK15:       omp.inner.for.inc:
1926 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1927 // CHECK15-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1
1928 // CHECK15-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1929 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1930 // CHECK15:       omp.inner.for.end:
1931 // CHECK15-NEXT:    store i32 10, ptr [[I]], align 4
1932 // CHECK15-NEXT:    store i32 2, ptr [[J]], align 4
1933 // CHECK15-NEXT:    ret i32 0
1934 //