[RISCV] Add MIPS P8700 processor (#119882)
[llvm-project.git] / flang / test / Lower / Intrinsics / ieee_is_finite.f90
blobee7d8dab7b9921b2e27d3eb6e54c4feef26312e3
1 ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s
3 ! CHECK-LABEL: c.func @_QPis_finite_test
4 subroutine is_finite_test(x, y)
5 use ieee_arithmetic, only: ieee_is_finite
6 real(4) x
7 real(8) y
9 ! CHECK: %[[V_3:[0-9]+]] = fir.load %arg0 : !fir.ref<f32>
10 ! CHECK: %[[V_4:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_3]]) <{bit = 504 : i32}> : (f32) -> i1
11 ! CHECK: %[[V_5:[0-9]+]] = fir.convert %[[V_4]] : (i1) -> !fir.logical<4>
12 ! CHECK: %[[V_6:[0-9]+]] = fir.convert %[[V_5]] : (!fir.logical<4>) -> i1
13 ! CHECK: %[[V_7:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_6]]) {{.*}} : (!fir.ref<i8>, i1) -> i1
14 print*, ieee_is_finite(x)
16 ! CHECK: %[[V_12:[0-9]+]] = fir.load %arg0 : !fir.ref<f32>
17 ! CHECK: %[[V_13:[0-9]+]] = fir.load %arg0 : !fir.ref<f32>
18 ! CHECK: %[[V_14:[0-9]+]] = arith.addf %[[V_12]], %[[V_13]] {{.*}} : f32
19 ! CHECK: %[[V_15:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_14]]) <{bit = 504 : i32}> : (f32) -> i1
20 ! CHECK: %[[V_16:[0-9]+]] = fir.convert %[[V_15]] : (i1) -> !fir.logical<4>
21 ! CHECK: %[[V_17:[0-9]+]] = fir.convert %[[V_16]] : (!fir.logical<4>) -> i1
22 ! CHECK: %[[V_18:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_17]]) {{.*}} : (!fir.ref<i8>, i1) -> i1
23 print*, ieee_is_finite(x+x)
25 ! CHECK: %[[V_23:[0-9]+]] = fir.load %arg1 : !fir.ref<f64>
26 ! CHECK: %[[V_24:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_23]]) <{bit = 504 : i32}> : (f64) -> i1
27 ! CHECK: %[[V_25:[0-9]+]] = fir.convert %[[V_24]] : (i1) -> !fir.logical<4>
28 ! CHECK: %[[V_26:[0-9]+]] = fir.convert %[[V_25]] : (!fir.logical<4>) -> i1
29 ! CHECK: %[[V_27:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_26]]) {{.*}} : (!fir.ref<i8>, i1) -> i1
30 print*, ieee_is_finite(y)
32 ! CHECK: %[[V_32:[0-9]+]] = fir.load %arg1 : !fir.ref<f64>
33 ! CHECK: %[[V_33:[0-9]+]] = fir.load %arg1 : !fir.ref<f64>
34 ! CHECK: %[[V_34:[0-9]+]] = arith.addf %[[V_32]], %[[V_33]] {{.*}} : f64
35 ! CHECK: %[[V_35:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_34]]) <{bit = 504 : i32}> : (f64) -> i1
36 ! CHECK: %[[V_36:[0-9]+]] = fir.convert %[[V_35]] : (i1) -> !fir.logical<4>
37 ! CHECK: %[[V_37:[0-9]+]] = fir.convert %[[V_36]] : (!fir.logical<4>) -> i1
38 ! CHECK: %[[V_38:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_37]]) {{.*}} : (!fir.ref<i8>, i1) -> i1
39 print*, ieee_is_finite(y+y)
40 end subroutine is_finite_test
42 ! CHECK-LABEL: c.func @_QQmain
43 real(4) x
44 real(8) y
45 ! CHECK: %[[V_0:[0-9]+]] = fir.alloca f64 {adapt.valuebyref}
46 ! CHECK: %[[V_1:[0-9]+]] = fir.alloca f32 {adapt.valuebyref}
47 ! CHECK: %cst = arith.constant 3.40282347E+38 : f32
48 ! CHECK: fir.store %cst to %[[V_1]] : !fir.ref<f32>
49 ! CHECK: %cst_0 = arith.constant 1.7976931348623157E+308 : f64
50 ! CHECK: fir.store %cst_0 to %[[V_0]] : !fir.ref<f64>
51 ! CHECK: fir.call @_QPis_finite_test(%[[V_1]], %[[V_0]]) {{.*}} : (!fir.ref<f32>, !fir.ref<f64>) -> ()
52 call is_finite_test(huge(x), huge(y))
53 end