[ELF] Make section member orders consistent
[llvm-project.git] / lld / test / ELF / aarch64-cortex-a53-843419-tlsrelax.s
blob9dffea5d653862383d530c4346371351d6560407
1 // REQUIRES: aarch64
2 // RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o
3 // RUN: ld.lld -fix-cortex-a53-843419 %t.o -o %t2
4 // RUN: llvm-objdump --no-print-imm-hex --triple=aarch64-linux-gnu -d %t2 | FileCheck %s
6 // The following code sequence is covered by the TLS IE to LE relaxation. It
7 // transforms the ADRP, LDR to MOVZ, MOVK. The former can trigger a
8 // cortex-a53-843419 patch, whereas the latter can not. As both
9 // relaxation and patching transform instructions very late in the
10 // link there is a possibility of them both being simultaneously
11 // applied. In this case the relaxed sequence is immune from the erratum so we
12 // prefer to keep it.
13 .text
14 .balign 4096
15 .space 4096 - 8
16 .globl _start
17 .type _start,@function
18 _start:
19 mrs x1, tpidr_el0
20 adrp x0, :gottprel:v
21 ldr x1, [x0, #:gottprel_lo12:v]
22 adrp x0, :gottprel:v
23 ldr x1, [x0, #:gottprel_lo12:v]
24 ret
26 // CHECK: <_start>:
27 // CHECK-NEXT: 211ff8: d53bd041 mrs x1, TPIDR_EL0
28 // CHECK-NEXT: 211ffc: d2a00000 movz x0, #0, lsl #16
29 // CHECK-NEXT: 212000: f2800201 movk x1, #16
30 // CHECK-NEXT: 212004: d2a00000 movz x0, #0, lsl #16
31 // CHECK-NEXT: 212008: f2800201 movk x1, #16
32 // CHECK-NEXT: 21200c: d65f03c0 ret
34 .type v,@object
35 .section .tbss,"awT",@nobits
36 .globl v
38 .word 0