[ELF] Make section member orders consistent
[llvm-project.git] / lld / test / ELF / arm-ldrlit.s
blobcd3918be47590342f79e23e78765b701f7f86981
1 // REQUIRES: arm
2 // RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
3 // RUN: echo "SECTIONS { \
4 // RUN: .rodata.low 0x8012 : { *(.rodata.low) } \
5 // RUN: .text.low 0x8f00 : { *(.text.low) } \
6 // RUN: .text.neg 0x9000 : { *(.text.neg) } \
7 // RUN: .text.pos 0x10000 : { *(.text.pos) } \
8 // RUN: .text.high 0x10100 : { *(.text.high) } \
9 // RUN: .data_high 0x1100f : { *(.data.high) } \
10 // RUN: } " > %t.script
11 // RUN: ld.lld -n --script %t.script %t.o -o %t
12 // RUN: llvm-readobj --symbols %t | FileCheck %s --check-prefix=SYMS
13 // RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
15 /// Test the various legal cases for the R_ARM_LDR_PC_G0 relocation
16 /// Range is +- 4095 bytes
17 /// The Thumb bit for function symbols is ignored
18 .section .rodata.low, "a", %progbits
19 dat1:
20 .byte 0
21 dat2:
22 .byte 1
23 dat3:
24 .byte 2
25 dat4:
26 .byte 3
28 .section .text.low, "ax", %progbits
29 .balign 4
30 .global target1
31 .type target1, %function
32 target1:
33 bx lr
34 .type target2, %function
35 target2:
36 bx lr
38 .section .text.neg, "ax", %progbits
39 .balign 4
40 .global _start
41 .type _start, %function
42 _start:
43 /// ldr r0, dat1
44 .inst 0xe51f0008
45 .reloc 0, R_ARM_LDR_PC_G0, dat1
46 /// ldr r1, dat2
47 .inst 0xe51f1008
48 .reloc 4, R_ARM_LDR_PC_G0, dat2
49 /// ldr r2, dat3
50 .inst 0xe51f2008
51 .reloc 8, R_ARM_LDR_PC_G0, dat3
52 /// ldr r3, dat4
53 .inst 0xe51f3008
54 .reloc 0xc, R_ARM_LDR_PC_G0, dat4
55 /// ldr r0, target1
56 .inst 0xe51f0008
57 .reloc 0x10, R_ARM_LDR_PC_G0, target1
58 /// ldr r1, target2
59 .inst 0xe51f1008
60 .reloc 0x14, R_ARM_LDR_PC_G0, target2
62 .section .text.pos, "ax", %progbits
63 .balign 4
64 .global pos
65 .type pos, %function
66 pos:
67 /// ldr r2, target3
68 .inst 0xe51f2008
69 .reloc 0, R_ARM_LDR_PC_G0, target3
70 /// ldr r3, target4
71 .inst 0xe51f3008
72 .reloc 4, R_ARM_LDR_PC_G0, target4
73 /// ldr r0, dat5
74 .inst 0xe51f0008
75 .reloc 8, R_ARM_LDR_PC_G0, dat5
76 /// ldr r1, dat6
77 .inst 0xe51f1008
78 .reloc 0xc, R_ARM_LDR_PC_G0, dat6
79 /// ldr r2, dat7
80 .inst 0xe51f2008
81 .reloc 0x10, R_ARM_LDR_PC_G0, dat7
82 /// ldr r3, dat8
83 .inst 0xe51f3008
84 .reloc 0x14, R_ARM_LDR_PC_G0, dat8
86 /// positive addend in instruction, all others are -4 (PC bias)
87 ///ldr r4, dat5 + 8
88 .inst 0xe59f4000
89 .reloc 0x18, R_ARM_LDR_PC_G0, dat5
91 .section .text.high, "ax", %progbits
92 .balign 4
93 .type target3, %function
94 .global target3
95 target3:
96 bx lr
97 .thumb_func
98 target4:
99 bx lr
101 .section .data.high, "aw", %progbits
102 dat5:
103 .byte 0
104 dat6:
105 .byte 1
106 dat7:
107 .byte 2
108 dat8:
109 .byte 3
111 // SYMS: Name: dat1
112 // SYMS-NEXT: Value: 0x8012
113 // SYMS: Name: dat2
114 // SYMS-NEXT: Value: 0x8013
115 // SYMS: Name: dat3
116 // SYMS-NEXT: Value: 0x8014
117 // SYMS: Name: dat4
118 // SYMS-NEXT: Value: 0x8015
120 // CHECK: 00008f00 <target1>:
121 // CHECK-NEXT: 8f00: bx lr
123 // CHECK: 00008f04 <target2>:
124 // CHECK-NEXT: 8f04: bx lr
126 // CHECK: 00009000 <_start>:
127 /// 0x9000 + 0x8 - 0xff6 = 0x8012
128 // CHECK-NEXT: 9000: ldr r0, [pc, #-4086]
129 /// 0x9004 + 0x8 - 0xff9 = 0x8013
130 // CHECK-NEXT: 9004: ldr r1, [pc, #-4089]
131 /// 0x9008 + 0x8 - 0xffc = 0x8014
132 // CHECK-NEXT: 9008: ldr r2, [pc, #-4092]
133 /// 0x900c + 0x8 - 0xfff = 0x8015
134 // CHECK-NEXT: 900c: ldr r3, [pc, #-4095]
135 /// 0x9010 + 0x8 - 0x118 = 0x8f00
136 // CHECK-NEXT: 9010: ldr r0, [pc, #-280]
137 /// 0x9014 + 0x8 - 0x118 = 0x8f04
138 // CHECK-NEXT: 9014: ldr r1, [pc, #-280]
140 // CHECK: 00010000 <pos>:
141 /// 0x10000 + 0x8 + 0xf8 = 0x10100
142 // CHECK-NEXT: 10000: ldr r2, [pc, #248]
143 /// 0x10004 + 0x8 + 0xf8 = 0x10104
144 // CHECK-NEXT: 10004: ldr r3, [pc, #248]
145 /// 0x10008 + 0x8 + 0xfff = 0x1100f
146 // CHECK-NEXT: 10008: ldr r0, [pc, #4095]
147 /// 0x1000c + 0x8 + 0xffc = 0x11010
148 // CHECK-NEXT: 1000c: ldr r1, [pc, #4092]
149 /// 0x10010 + 0x8 + 0xff9 = 0x11011
150 // CHECK-NEXT: 10010: ldr r2, [pc, #4089]
151 /// 0x10014 + 0x8 + 0xff6 = 0x11012
152 // CHECK-NEXT: 10014: ldr r3, [pc, #4086]
153 /// 0x10018 + 0x8 + 0xff7 = 0x11017 = dat5 + 8
154 // CHECK-NEXT: 10018: ldr r4, [pc, #4087]
156 // CHECK: 00010100 <target3>:
157 // CHECK-NEXT: 10100: bx lr
159 // CHECK: 00010104 <target4>:
160 // CHECK-NEXT: 10104: bx lr
162 // SYMS: Name: dat5
163 // SYMS-NEXT: Value: 0x1100F
164 // SYMS: Name: dat6
165 // SYMS-NEXT: Value: 0x11010
166 // SYMS: Name: dat7
167 // SYMS-NEXT: Value: 0x11011
168 // SYMS: Name: dat8
169 // SYMS-NEXT: Value: 0x11012