llvm/lib/Target/RISCV/RISCVProcessors.td

   1 //===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // RISC-V processors supported.
  11 //===----------------------------------------------------------------------===//
  12
  13 class RISCVTuneInfo {
  14   bits<8> PrefFunctionAlignment = 1;
  15   bits<8> PrefLoopAlignment = 1;
  16
  17   // Information needed by LoopDataPrefetch.
  18   bits<16> CacheLineSize = 0;
  19   bits<16> PrefetchDistance = 0;
  20   bits<16> MinPrefetchStride = 1;
  21   bits<32> MaxPrefetchIterationsAhead = -1;
  22
  23   bits<32> MinimumJumpTableEntries = 5;
  24
  25   // Tail duplication threshold at -O3.
  26   bits<32> TailDupAggressiveThreshold = 6;
  27
  28   bits<32> MaxStoresPerMemsetOptSize = 4;
  29   bits<32> MaxStoresPerMemset = 8;
  30
  31   bits<32> MaxGluedStoresPerMemcpy = 0;
  32   bits<32> MaxStoresPerMemcpyOptSize = 4;
  33   bits<32> MaxStoresPerMemcpy = 8;
  34
  35   bits<32> MaxStoresPerMemmoveOptSize = 4;
  36   bits<32> MaxStoresPerMemmove = 8;
  37
  38   bits<32> MaxLoadsPerMemcmpOptSize = 4;
  39   bits<32> MaxLoadsPerMemcmp = 8;
  40 }
  41
  42 def RISCVTuneInfoTable : GenericTable {
  43   let FilterClass = "RISCVTuneInfo";
  44   let CppTypeName = "RISCVTuneInfo";
  45   let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
  46                 "CacheLineSize", "PrefetchDistance", "MinPrefetchStride",
  47                 "MaxPrefetchIterationsAhead", "MinimumJumpTableEntries",
  48                 "TailDupAggressiveThreshold", "MaxStoresPerMemsetOptSize",
  49                 "MaxStoresPerMemset", "MaxGluedStoresPerMemcpy",
  50                 "MaxStoresPerMemcpyOptSize", "MaxStoresPerMemcpy",
  51                 "MaxStoresPerMemmoveOptSize", "MaxStoresPerMemmove",
  52                 "MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp"];
  53 }
  54
  55 def getRISCVTuneInfo : SearchIndex {
  56   let Table = RISCVTuneInfoTable;
  57   let Key = ["Name"];
  58 }
  59
  60 class GenericTuneInfo: RISCVTuneInfo;
  61
  62 class RISCVProcessorModel<string n,
  63                           SchedMachineModel m,
  64                           list<SubtargetFeature> f,
  65                           list<SubtargetFeature> tunef = [],
  66                           string default_march = "">
  67     :  ProcessorModel<n, m, f, tunef> {
  68   string DefaultMarch = default_march;
  69   int MVendorID = 0;
  70   int MArchID = 0;
  71   int MImpID = 0;
  72 }
  73
  74 class RISCVTuneProcessorModel<string n,
  75                               SchedMachineModel m,
  76                               list<SubtargetFeature> tunef = [],
  77                               list<SubtargetFeature> f = []>
  78     : ProcessorModel<n, m, f,tunef>;
  79
  80 defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
  81
  82 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
  83                                        NoSchedModel,
  84                                        [Feature32Bit,
  85                                         FeatureStdExtI],
  86                                        GenericTuneFeatures>,
  87                    GenericTuneInfo;
  88 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
  89                                        NoSchedModel,
  90                                        [Feature64Bit,
  91                                         FeatureStdExtI],
  92                                        GenericTuneFeatures>,
  93                    GenericTuneInfo;
  94 // Support generic for compatibility with other targets. The triple will be used
  95 // to change to the appropriate rv32/rv64 version.
  96 def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
  97
  98 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
  99                                       RocketModel,
 100                                       [Feature32Bit,
 101                                        FeatureStdExtI,
 102                                        FeatureStdExtZifencei,
 103                                        FeatureStdExtZicsr]>;
 104 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
 105                                       RocketModel,
 106                                       [Feature64Bit,
 107                                        FeatureStdExtI,
 108                                        FeatureStdExtZifencei,
 109                                        FeatureStdExtZicsr]>;
 110 def ROCKET : RISCVTuneProcessorModel<"rocket",
 111                                      RocketModel>;
 112
 113 defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll,
 114                               TuneShortForwardBranchOpt,
 115                               TunePostRAScheduler];
 116 def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
 117                                        SiFive7Model, SiFive7TuneFeatures>;
 118
 119 def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
 120                                      RocketModel,
 121                                      [Feature32Bit,
 122                                       FeatureStdExtI,
 123                                       FeatureStdExtZicsr,
 124                                       FeatureStdExtZifencei,
 125                                       FeatureStdExtM,
 126                                       FeatureStdExtC]>;
 127
 128 def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
 129                                      RocketModel,
 130                                      [Feature32Bit,
 131                                       FeatureStdExtI,
 132                                       FeatureStdExtZicsr,
 133                                       FeatureStdExtZifencei,
 134                                       FeatureStdExtM,
 135                                       FeatureStdExtA,
 136                                       FeatureStdExtC]>;
 137
 138 def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
 139                                      RocketModel,
 140                                      [Feature32Bit,
 141                                       FeatureStdExtI,
 142                                       FeatureStdExtZifencei,
 143                                       FeatureStdExtM,
 144                                       FeatureStdExtA,
 145                                       FeatureStdExtF,
 146                                       FeatureStdExtC]>;
 147
 148 def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
 149                                      RocketModel,
 150                                      [Feature32Bit,
 151                                       FeatureStdExtI,
 152                                       FeatureStdExtZifencei,
 153                                       FeatureStdExtZicsr,
 154                                       FeatureStdExtM,
 155                                       FeatureStdExtA,
 156                                       FeatureStdExtC]>;
 157
 158 def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
 159                                      RocketModel,
 160                                      [Feature32Bit,
 161                                       FeatureStdExtI,
 162                                       FeatureStdExtZifencei,
 163                                       FeatureStdExtM,
 164                                       FeatureStdExtA,
 165                                       FeatureStdExtF,
 166                                       FeatureStdExtC]>;
 167
 168 def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
 169                                      SiFive7Model,
 170                                      [Feature32Bit,
 171                                       FeatureStdExtI,
 172                                       FeatureStdExtZifencei,
 173                                       FeatureStdExtM,
 174                                       FeatureStdExtA,
 175                                       FeatureStdExtF,
 176                                       FeatureStdExtC],
 177                                      SiFive7TuneFeatures>;
 178
 179 def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
 180                                      RocketModel,
 181                                      [Feature64Bit,
 182                                       FeatureStdExtI,
 183                                       FeatureStdExtZicsr,
 184                                       FeatureStdExtZifencei,
 185                                       FeatureStdExtM,
 186                                       FeatureStdExtA,
 187                                       FeatureStdExtC]>;
 188
 189 def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
 190                                      RocketModel,
 191                                      [Feature64Bit,
 192                                       FeatureStdExtI,
 193                                       FeatureStdExtZicsr,
 194                                       FeatureStdExtZifencei,
 195                                       FeatureStdExtM,
 196                                       FeatureStdExtA,
 197                                       FeatureStdExtC]>;
 198
 199 def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
 200                                       RocketModel,
 201                                       [Feature64Bit,
 202                                        FeatureStdExtI,
 203                                        FeatureStdExtZifencei,
 204                                        FeatureStdExtM,
 205                                        FeatureStdExtA,
 206                                        FeatureStdExtF,
 207                                        FeatureStdExtD,
 208                                        FeatureStdExtC]>;
 209
 210 def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
 211                                      SiFive7Model,
 212                                      [Feature64Bit,
 213                                       FeatureStdExtI,
 214                                       FeatureStdExtZifencei,
 215                                       FeatureStdExtM,
 216                                       FeatureStdExtA,
 217                                       FeatureStdExtF,
 218                                       FeatureStdExtD,
 219                                       FeatureStdExtC,
 220                                       FeatureStdExtZihintpause],
 221                                      SiFive7TuneFeatures>;
 222
 223 def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
 224                                      RocketModel,
 225                                      [Feature64Bit,
 226                                       FeatureStdExtI,
 227                                       FeatureStdExtZifencei,
 228                                       FeatureStdExtM,
 229                                       FeatureStdExtA,
 230                                       FeatureStdExtF,
 231                                       FeatureStdExtD,
 232                                       FeatureStdExtC]>;
 233
 234 def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
 235                                      SiFive7Model,
 236                                      [Feature64Bit,
 237                                       FeatureStdExtI,
 238                                       FeatureStdExtZifencei,
 239                                       FeatureStdExtM,
 240                                       FeatureStdExtA,
 241                                       FeatureStdExtF,
 242                                       FeatureStdExtD,
 243                                       FeatureStdExtC],
 244                                      SiFive7TuneFeatures>;
 245
 246 defvar SiFiveX280TuneFeatures = !listconcat(SiFive7TuneFeatures,
 247                                             [TuneDLenFactor2,
 248                                              TuneOptimizedZeroStrideLoad,
 249                                              TuneOptimizedNF2SegmentLoadStore]);
 250 def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
 251                                       [Feature64Bit,
 252                                        FeatureStdExtI,
 253                                        FeatureStdExtZifencei,
 254                                        FeatureStdExtM,
 255                                        FeatureStdExtA,
 256                                        FeatureStdExtF,
 257                                        FeatureStdExtD,
 258                                        FeatureStdExtC,
 259                                        FeatureStdExtV,
 260                                        FeatureStdExtZvl512b,
 261                                        FeatureStdExtZfh,
 262                                        FeatureStdExtZvfh,
 263                                        FeatureStdExtZba,
 264                                        FeatureStdExtZbb],
 265                                       SiFiveX280TuneFeatures>;
 266
 267 defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
 268                                  TuneConditionalCompressedMoveFusion,
 269                                  TuneLUIADDIFusion,
 270                                  TuneAUIPCADDIFusion,
 271                                  TunePostRAScheduler];
 272
 273 def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
 274                                       !listconcat(RVA22U64Features,
 275                                       [FeatureStdExtZifencei,
 276                                        FeatureStdExtZihintntl,
 277                                        FeatureUnalignedScalarMem,
 278                                        FeatureUnalignedVectorMem]),
 279                                       SiFiveP400TuneFeatures>;
 280
 281 def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
 282                                       !listconcat(RVA22U64Features,
 283                                       [FeatureStdExtV,
 284                                        FeatureStdExtZifencei,
 285                                        FeatureStdExtZihintntl,
 286                                        FeatureStdExtZvl128b,
 287                                        FeatureStdExtZvbb,
 288                                        FeatureStdExtZvknc,
 289                                        FeatureStdExtZvkng,
 290                                        FeatureStdExtZvksc,
 291                                        FeatureStdExtZvksg,
 292                                        FeatureVendorXSiFivecdiscarddlone,
 293                                        FeatureVendorXSiFivecflushdlone,
 294                                        FeatureUnalignedScalarMem,
 295                                        FeatureUnalignedVectorMem]),
 296                                       !listconcat(SiFiveP400TuneFeatures,
 297                                                   [TuneNoSinkSplatOperands,
 298                                                    TuneVXRMPipelineFlush])>;
 299
 300
 301 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
 302                                       !listconcat(RVA22U64Features,
 303                                       [FeatureStdExtV,
 304                                        FeatureStdExtZifencei,
 305                                        FeatureStdExtZihintntl,
 306                                        FeatureStdExtZvl128b,
 307                                        FeatureStdExtZvbb,
 308                                        FeatureStdExtZvknc,
 309                                        FeatureStdExtZvkng,
 310                                        FeatureStdExtZvksc,
 311                                        FeatureStdExtZvksg,
 312                                        FeatureUnalignedScalarMem,
 313                                        FeatureUnalignedVectorMem]),
 314                                       [TuneNoDefaultUnroll,
 315                                        TuneConditionalCompressedMoveFusion,
 316                                        TuneLUIADDIFusion,
 317                                        TuneAUIPCADDIFusion,
 318                                        TuneNoSinkSplatOperands,
 319                                        TuneVXRMPipelineFlush,
 320                                        TunePostRAScheduler]>;
 321
 322 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
 323                                               SyntacoreSCR1Model,
 324                                               [Feature32Bit,
 325                                                FeatureStdExtI,
 326                                                FeatureStdExtZicsr,
 327                                                FeatureStdExtZifencei,
 328                                                FeatureStdExtC],
 329                                               [TuneNoDefaultUnroll]>;
 330
 331 def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
 332                                              SyntacoreSCR1Model,
 333                                              [Feature32Bit,
 334                                               FeatureStdExtI,
 335                                               FeatureStdExtZicsr,
 336                                               FeatureStdExtZifencei,
 337                                               FeatureStdExtM,
 338                                               FeatureStdExtC],
 339                                              [TuneNoDefaultUnroll]>;
 340
 341 def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
 342                                               SyntacoreSCR3RV32Model,
 343                                               [Feature32Bit,
 344                                                FeatureStdExtI,
 345                                                FeatureStdExtZicsr,
 346                                                FeatureStdExtZifencei,
 347                                                FeatureStdExtM,
 348                                                FeatureStdExtC],
 349                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 350
 351 def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
 352                                               SyntacoreSCR3RV64Model,
 353                                               [Feature64Bit,
 354                                                FeatureStdExtI,
 355                                                FeatureStdExtZicsr,
 356                                                FeatureStdExtZifencei,
 357                                                FeatureStdExtM,
 358                                                FeatureStdExtA,
 359                                                FeatureStdExtC],
 360                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 361
 362 def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
 363                                               SyntacoreSCR4RV32Model,
 364                                               [Feature32Bit,
 365                                                FeatureStdExtI,
 366                                                FeatureStdExtZicsr,
 367                                                FeatureStdExtZifencei,
 368                                                FeatureStdExtM,
 369                                                FeatureStdExtF,
 370                                                FeatureStdExtD,
 371                                                FeatureStdExtC],
 372                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 373
 374 def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
 375                                               SyntacoreSCR4RV64Model,
 376                                               [Feature64Bit,
 377                                                FeatureStdExtI,
 378                                                FeatureStdExtZicsr,
 379                                                FeatureStdExtZifencei,
 380                                                FeatureStdExtM,
 381                                                FeatureStdExtA,
 382                                                FeatureStdExtF,
 383                                                FeatureStdExtD,
 384                                                FeatureStdExtC],
 385                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 386
 387 def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
 388                                               SyntacoreSCR5RV32Model,
 389                                               [Feature32Bit,
 390                                                FeatureStdExtI,
 391                                                FeatureStdExtZicsr,
 392                                                FeatureStdExtZifencei,
 393                                                FeatureStdExtM,
 394                                                FeatureStdExtA,
 395                                                FeatureStdExtF,
 396                                                FeatureStdExtD,
 397                                                FeatureStdExtC],
 398                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 399
 400 def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
 401                                               SyntacoreSCR5RV64Model,
 402                                               [Feature64Bit,
 403                                                FeatureStdExtI,
 404                                                FeatureStdExtZicsr,
 405                                                FeatureStdExtZifencei,
 406                                                FeatureStdExtM,
 407                                                FeatureStdExtA,
 408                                                FeatureStdExtF,
 409                                                FeatureStdExtD,
 410                                                FeatureStdExtC],
 411                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 412
 413 def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
 414                                               SyntacoreSCR7Model,
 415                                               [Feature64Bit,
 416                                                FeatureStdExtI,
 417                                                FeatureStdExtZicsr,
 418                                                FeatureStdExtZifencei,
 419                                                FeatureStdExtM,
 420                                                FeatureStdExtA,
 421                                                FeatureStdExtF,
 422                                                FeatureStdExtD,
 423                                                FeatureStdExtC,
 424                                                FeatureStdExtV,
 425                                                FeatureStdExtZba,
 426                                                FeatureStdExtZbb,
 427                                                FeatureStdExtZbc,
 428                                                FeatureStdExtZbs,
 429                                                FeatureStdExtZkn],
 430                                               [TuneNoDefaultUnroll, TunePostRAScheduler]>;
 431
 432 def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
 433                                                  NoSchedModel,
 434                                                  !listconcat(RVA23S64Features,
 435                                                  [FeatureStdExtSmaia,
 436                                                   FeatureStdExtSsaia,
 437                                                   FeatureStdExtSscofpmf,
 438                                                   FeatureStdExtSsstrict,
 439                                                   FeatureStdExtZfbfmin,
 440                                                   FeatureStdExtZfh,
 441                                                   FeatureStdExtZicsr,
 442                                                   FeatureStdExtZvbc,
 443                                                   FeatureStdExtZvfbfmin,
 444                                                   FeatureStdExtZvfbfwma,
 445                                                   FeatureStdExtZvfh,
 446                                                   FeatureStdExtZvkng,
 447                                                   FeatureStdExtZvl256b,
 448                                                   FeatureUnalignedScalarMem,
 449                                                   FeatureUnalignedVectorMem]),
 450                                                  [TuneNoDefaultUnroll,
 451                                                   TuneOptimizedZeroStrideLoad,
 452                                                   TunePostRAScheduler]>;
 453
 454 def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
 455                                             NoSchedModel,
 456                                             [Feature64Bit,
 457                                              FeatureStdExtI,
 458                                              FeatureStdExtZifencei,
 459                                              FeatureStdExtZicsr,
 460                                              FeatureStdExtZicntr,
 461                                              FeatureStdExtZihpm,
 462                                              FeatureStdExtZihintpause,
 463                                              FeatureStdExtM,
 464                                              FeatureStdExtA,
 465                                              FeatureStdExtF,
 466                                              FeatureStdExtD,
 467                                              FeatureStdExtC,
 468                                              FeatureStdExtZba,
 469                                              FeatureStdExtZbb,
 470                                              FeatureStdExtZbc,
 471                                              FeatureStdExtZbs,
 472                                              FeatureStdExtZicbom,
 473                                              FeatureStdExtZicbop,
 474                                              FeatureStdExtZicboz,
 475                                              FeatureVendorXVentanaCondOps],
 476                                              [TuneVentanaVeyron,
 477                                               TuneLUIADDIFusion,
 478                                               TuneAUIPCADDIFusion,
 479                                               TuneZExtHFusion,
 480                                               TuneZExtWFusion,
 481                                               TuneShiftedZExtWFusion,
 482                                               TuneLDADDFusion]> {
 483   let MVendorID = 0x61f;
 484   let MArchID = 0x8000000000010000;
 485   let MImpID = 0x111;
 486 }
 487
 488 def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
 489                                           XiangShanNanHuModel,
 490                                           [Feature64Bit,
 491                                            FeatureStdExtI,
 492                                            FeatureStdExtZicsr,
 493                                            FeatureStdExtZifencei,
 494                                            FeatureStdExtM,
 495                                            FeatureStdExtA,
 496                                            FeatureStdExtF,
 497                                            FeatureStdExtD,
 498                                            FeatureStdExtC,
 499                                            FeatureStdExtZba,
 500                                            FeatureStdExtZbb,
 501                                            FeatureStdExtZbc,
 502                                            FeatureStdExtZbs,
 503                                            FeatureStdExtZkn,
 504                                            FeatureStdExtZksed,
 505                                            FeatureStdExtZksh,
 506                                            FeatureStdExtSvinval,
 507                                            FeatureStdExtZicbom,
 508                                            FeatureStdExtZicboz],
 509                                            [TuneNoDefaultUnroll,
 510                                             TuneZExtHFusion,
 511                                             TuneZExtWFusion,
 512                                             TuneShiftedZExtWFusion]>;
 513
 514 def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
 515                                        NoSchedModel,
 516                                        !listconcat(RVA22S64Features,
 517                                        [FeatureStdExtV,
 518                                         FeatureStdExtSscofpmf,
 519                                         FeatureStdExtSstc,
 520                                         FeatureStdExtSvnapot,
 521                                         FeatureStdExtZbc,
 522                                         FeatureStdExtZbkc,
 523                                         FeatureStdExtZfh,
 524                                         FeatureStdExtZicond,
 525                                         FeatureStdExtZvfh,
 526                                         FeatureStdExtZvkt,
 527                                         FeatureStdExtZvl256b,
 528                                         FeatureUnalignedScalarMem]),
 529                                        [TuneDLenFactor2,
 530                                         TuneOptimizedNF2SegmentLoadStore,
 531                                         TuneOptimizedNF3SegmentLoadStore,
 532                                         TuneOptimizedNF4SegmentLoadStore,
 533                                         TuneVXRMPipelineFlush]> {
 534   let MVendorID = 0x710;
 535   let MArchID = 0x8000000058000001;
 536   let MImpID = 0x1000000049772200;
 537 }
 538
 539 def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
 540                                          NoSchedModel,
 541                                          [Feature32Bit,
 542                                           FeatureStdExtI,
 543                                           FeatureStdExtM,
 544                                           FeatureStdExtA,
 545                                           FeatureStdExtC,
 546                                           FeatureStdExtZicsr,
 547                                           FeatureStdExtZifencei,
 548                                           FeatureStdExtZba,
 549                                           FeatureStdExtZbb,
 550                                           FeatureStdExtZbs,
 551                                           FeatureStdExtZbkb,
 552                                           FeatureStdExtZcb,
 553                                           FeatureStdExtZcmp]>;