1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4 name: test_constant_vec_pool_v2f64
8 tracksRegLiveness: true
13 machineFunctionInfo: {}
18 ; CHECK-LABEL: name: test_constant_vec_pool_v2f64
20 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
21 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
22 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
23 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
26 %3:fpr(s64) = G_FCONSTANT double 5.000000e-01
27 %2:fpr(s64) = G_FCONSTANT double 1.600000e+01
28 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
29 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
34 name: test_constant_vec_pool_v4f32
38 tracksRegLiveness: true
47 ; CHECK-LABEL: name: test_constant_vec_pool_v4f32
49 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
50 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
51 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
52 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
55 %3:fpr(s32) = G_FCONSTANT float 5.000000e-01
56 %2:fpr(s32) = G_FCONSTANT float 1.600000e+01
57 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)
58 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
63 name: test_constant_vec_pool_v2i64
67 tracksRegLiveness: true
76 ; CHECK-LABEL: name: test_constant_vec_pool_v2i64
78 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
79 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
80 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
81 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
84 %3:gpr(s64) = G_CONSTANT i64 67839
85 %2:gpr(s64) = G_CONSTANT i64 12375
86 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
87 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
92 name: test_constant_vec_pool_v4i32
96 tracksRegLiveness: true
105 ; CHECK-LABEL: name: test_constant_vec_pool_v4i32
106 ; CHECK: liveins: $x0
107 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
108 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
109 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
110 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
111 ; CHECK: RET_ReallyLR
112 %0:gpr(p0) = COPY $x0
113 %3:gpr(s32) = G_CONSTANT i32 67839
114 %2:gpr(s32) = G_CONSTANT i32 12375
115 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)
116 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
122 name: test_constant_vec_pool_v2i32
125 regBankSelected: true
126 tracksRegLiveness: true
135 ; CHECK-LABEL: name: test_constant_vec_pool_v2i32
136 ; CHECK: liveins: $x0
137 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
138 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
139 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
140 ; CHECK: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))
141 ; CHECK: RET_ReallyLR
142 %0:gpr(p0) = COPY $x0
143 %3:gpr(s32) = G_CONSTANT i32 67839
144 %2:gpr(s32) = G_CONSTANT i32 12375
145 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)
146 G_STORE %1(<2 x s32>), %0(p0) :: (store (<2 x s32>))